Z87010 Datasheet, PDF (17/22 Pages) Zilog, Inc. – Audio Encoder/Decoders

Zilog
Z87010/Z87L10
Audio Encoder/Decoders
Assuming an input clock of 16.384 MHz, SCLK is pro- FS0, FS1 (Frame Sync)
grammed by the Z87010 embedded software for 2.048 The Frame Sync is used for enabling data transfer/receive.
MHz.
TXD (Serial Output to CODEC)
The rising and falling edge of the Frame Sync encloses the
serial data transmission. The Z87010 embedded software
2
programs the Frame Sync signal to 8 kHz.
The TXD line provides 8-bit data transfers. Each bit is
clocked out of the processor by the rising edge of the Interrupt
SCLK, with the MSB transmitted first.
Once the transmission of serial data is completed an inter-
nal interrupt signal is initiated. A single-cycle Low pulse
RXD (Serial Input from CODEC)
provides an interrupt on INT1. When this occurs, the pro-
The RXD line provides 8-bit data transfers. Each bit is _{cessor will jump to the defined Interrupt 1 vector location.}
clocked into the processor by the falling edge of the SCLK,
with the MSB received first.
/int1
fs1
fs0
sclk
txd
rxd
Figure 10. CODEC Interface Timing (8-Bit Mode)
CODEC Interface Timing
Figure 10 depicts a typical 8-bit serial data transfer using
both of the CODEC Interface Channels. The transmitting
data is clocked out on the rising edge of the SCLK signal.
An external CODEC clocks data in on the falling edge of
the SCLK signal. Once the serial data is transmitted, an in-
terrupt is given. The CODEC interface signals are not initi-
ated if the CODEC interface is not enabled.
The following modes are available for FSYNC and SCLK
signals:
SCLK
Internal
External
External
Internal
FSYNC
Internal
External
Internal
External
DS96WRL0601
PRELIMINARY
2-17