Z87010 Datasheet, PDF (15/22 Pages) Zilog, Inc. – Audio Encoder/Decoders

Zilog
Z87010/Z87L10
Audio Encoder/Decoders
FUNCTIONAL DESCRIPTION
General functional partitioning of the Z87010 is shown in User Outputs. The status register bits S5 and S6 connect
2 ^{Figure 1. The chip consists of the Z89S00 static DSP core directly to UO0 and UO1 pins and may be written to by the}
with 512 words of RAM, 4K words of ROM, a CODEC in- appropriate instruction. Note: The user output value is the
terface, a general-purpose timer and a wait state genera- opposite of the status register content.
tor.
I/O Bus. The Z87010 provides a 16-bit, CMOS compatible
The DSP core is characterized by an efficient hardware ar- I/O bus. I/O Control pins provide convenient communica-
chitecture that allows fast arithmetic operations such as tion capabilities with external peripherals. Single cycle ac-
multiplication, addition, subtraction and multiply-accumu- cess is possible. For slower communications, an on-board
late of two 16-bit operands. Most instructions are executed hardware wait-state generator can be used to accommo-
in one clock cycle.
date timing conflicts.
The DSP core uses a RAM memory of 512 16-bit words di-
vided in two banks.
Program Memory. The Z87010 has a 4K 16-bit words in-
ternal ROM including 4 words for interrupt and reset vec-
tors. The ROM is mapped at address 0000H to 0FFFH.
The reset vector is located at address 0FFCH, interrupts
INT0 is at 0FFDH, interrupt INT1 is at 0FFEH and interrupt
INT2 is at 0FFFH.
Interrupts. The Z87010 has three positive edge-triggered
interrupt inputs pins. However, INT1 is dedicated to the
CODEC interface and INT2 is dedicated to the 13-bit timer
if these peripherals are enabled.
These latched output address pins (EA0-2) allow a maxi-
mum of eight external peripherals. However up to four of
these addresses (EXT4-7) are used by internal peripherals
if enabled.
EXT4 13-bit Timer Configuration Register
EXT5 CODEC Interface Channel 0 Data
EXT6 CODEC Interface Channel 1 Data
EXT7 CODEC Interface Configuration Register and Wait
State Generator.
User Inputs. The Z87010 has two inputs, UI0 and UI1,
which may be used by Jump and Call instructions. The
Jump or Call tests one of these pins and if appropriate,
jumps to a new location. Otherwise, the instruction be-
haves like a NOP. These inputs are also connected to the
status register bits S10 and S11, which may be read by the
appropriate instruction.
DS96WRL0601
PRELIMINARY
2-15