Z87010 Datasheet, PDF (14/22 Pages) Zilog, Inc. – Audio Encoder/Decoders

Z87010/Z87L10
Audio Encoder/Decoders
Zilog
PIN FUNCTIONS
CK Clock (input). This pin controls the external clock.
EXT15-EXT0 External Data Bus (input/output). Data bus
for user-defined outside registers. The pins are normally
tri-stated, except when the outside registers are specified
as destination registers in the instructions. All the control
signals exist to allow a read or a write through this bus. The
bus is used for Z87000 interface.
ER//W External Bus Direction (output). Data direction sig-
nal for EXT-Bus. Data is available from the CPU on
EXT15-EXT0 when this signal is Low. EXT-Bus is in input
mode (high-impedance) when this signal is High.
EA2-EA0 External Address (output). User-defined register
address output (latched). One of eight user-defined exter-
nal registers is selected by the processor with these ad-
dresses are part of the processor memory map, the pro-
cessor is simply executing internal reads and writes.
External Addresses EXT4-EXT7 are used internally by the
processor if the CODEC interface and 13-bit timer are en-
abled.
/EI Enable Input (output). Read/Write timing signal for
EXT-Bus. User strobe is for triggering external peripheral.
Data is read by the external peripheral on the rising edge
of /EI. Data is read by the processor on the rising edge of
CK not /EI.
HALT Halt State (input). Stop Execution Control. The CPU
continuously executes NOPs and the program counter re-
mains at the same value when this pin is held High. This
signal must be synchronized with CK. An interrupt request
must be executed (enabled) to exit HALT mode. After the
interrupt service routine, the program continues from the
instruction after the HALT.
INT1 and INT2 are shared with internal Z87010 peripher-
als. INT1 is dedicated to the CODEC interface if enabled.
INT2 services the 13-bit Timer if enabled. In the Z87010
standard software configuration, INT0 and INT2 are not
used; INT1 is used by the CODEC interface.
/RES Reset (input, active Low). This pin controls the asyn-
chronous reset signal. The /RESET signal must be kept
Low for at least one clock cycle. The CPU pushes the con-
tents of the Program Counter (PC) onto the stack and then
fetches a new PC value from program memory address
0FFCH after the reset signal is released.
/RDYE Data Ready (input). User-supplied Data Ready sig-
nal for data to and from external data bus. This pin stretch-
es the /EI and ER//W lines and maintains data on the ad-
dress bus and data bus. The ready signal is sampled from
the rising clock only if ready is active. A single wait-state
can be generated internally by setting the appropriate bits
in the EXT7-2 register.
UI1-UI0 Two Input Pins (input). General-purpose input
pins. These input pins are directly tested by the conditional
branch instructions: and are reflected in two bits of the sta-
tus register (S10 and S11). These are asynchronous input
signals that have no special clock synchronization require-
ments.
U01-U00 Two Output Pins (push-pull output). General-
purpose output pins. These pins reflect the value of two
bits in the status register (S5 and S6). UO0 is dedicated to
provide an interrupt signal to the Z87000 controller. Note:
the user output pin values are the inverse of the status reg-
ister content.
/INT2-/INT0 Three Interrupts (input, active Low). Interrupt
request 2-0. Interrupts are generated on the rising edge of
the input signal. Interrupt vectors for the interrupt service
routine starting address are stored in the program memory
locations 0FFFH for /INT0, 0FFEH for /INT1, and 0FFFDH
for /INT2. Priorities are: INT2=Lowest, INT0=highest.
2-14
PRELIMINARY
DS96WRL0601