Z87010 Datasheet, PDF (20/22 Pages) Zilog, Inc. – Audio Encoder/Decoders

Z87010/Z87L10
Audio Encoder/Decoders
CODEC INTERFACE (Continued)
The CODEC Interface Control Register (EXT7-1) is shown
on Figure 13. Setting of the CODEC mode, FSYNC mode
and CODEC 0 enable/disable is done through this register.
A second control register (EXT7-2) also mapped on ad-
dress EXT7 control the CODEC 1, SCLK source and wait
state generator (see Figure 9). The “operation” section de-
scribes how to access the various register.
Wait-State Generator
An internal wait state generator is provided to accommo-
date slow external peripherals. One wait-state can be au-
tomatically inserted by the Z87010 in any EXT bus access.
Read and/or write cycles can be independently lengthened
for each register, by setting register EXT7-2 accordingly.
See Figure 9 for detailed description of EXT7-2.
The Z87010 software uses one wait state on all external
register accesses.
For additional wait states, a dedicate pin (/RDYE) can be
held high. The /RDYE pin is monitored only during execu-
tion of a Read or Write Instruction to external peripherals.
Zilog
General-Purpose Counter Timer
A 13-bit counter/timer is available for general-purpose use.
When the counter counts down to the zero state, an inter-
rupt is received on INT2. If the counter is disabled, EXT4
can be used as a general-purpose address. The counting
operation of the counter can be disabled by resetting bit
14. By selecting the clock source to the CODEC counter
output (FSYNC), one can extend the counter to a total of
26 bits.
Note: Placing zeroes into the Count Value register does
not generate an interrupt. Therefore it is possible to have
a single-pass option by loading the counter with zero after
the start of count.
The Counter is defaulted to the Enable state. If the system
designer does not choose to use the timer, the counter can
be disabled. Once disabled, the designer cannot enable
the counter unless a reset of the processor is performed.
Example:
LD EXT, #%C0008 1100 0000 0000 1000
; Enable Counter
; Enable Counting
; Clock Source = OSC/2
; Count Value = 1000=8
; Interrupt will occur every 16 clock
cycles
EXT4
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
* Default State
Figure 15. Timer Register
Count Value (Down-Counter)
Clock Source
0 Oscillator/2*
1 CODEC Counter Output
Count Operation
0 = Disable*
1 = Enable
Counter
0 = Disable
1 = Enable*
2-20
PRELIMINARY
DS96WRL0601