XC2C512 Datasheet, PDF (9/14 Pages) Xilinx, Inc – Industry’s best 0.18 micron CMOS CPLD

R
CoolRunner-II CPLD Family
CLK_CT
PTC
GCK0
GCK1
GCK2
PTC
D/T
Q
CE ^FIF
Latch
CK ^{✓DualEDGE}
DS090_09_121201
Figure 9: Macrocell Clock Chain with DualEDGE Option Shown
CTC
PTC
GCK0
GCK1
GCK2
PTC
D/T
Q
CE ^FIF
CK ^{✓LDautaclhEDGE}
GCK2
÷2
÷4
÷6
Clock ^÷8
In
÷10
÷12
÷14
÷16
Synch Rst
Synch Reset
DS090_10_121201
Figure 10: CoolCLOCK Created by Cascading Clock Divider and DualEDGE Option
Design Security
Designs can be secured during programming to prevent
either accidental overwriting or pattern theft via readback.
Four independent levels of security are provided on-chip,
eliminating any electrical or visual detection of configuration
patterns. These security bits can be reset only by erasing
the entire device. Additional detail is omitted intentionally.
Timing Model
Figure 11 shows the CoolRunner-II CPLD timing model. It
represents one aspect of the overall architecture from a tim-
ing viewpoint. Each little block is a time delay that a signal
will incur if the signal passes through such a resource. Tim-
ing reports are created by tallying the incremental signal
delays as signals progress within the CPLD. Software cre-
ates the timing reports after a design has been mapped
onto the specific part, and knows the specific delay values
for a given speed grade. Equations for the higher level tim-
ing values (i.e., T_PD and F_SYSTEM ) are available. Table 5
summarizes the individual parameters and provides a brief
definition of their associated functions. Xilinx application
note XAPP375 details the CoolRunner-II CPLD family tim-
ing with several examples.
DS090 (v1.7) October 2, 2003
www.xilinx.com
9
Preliminary Product Specification
1-800-255-7778