XC2C512 Datasheet, PDF(3/14 Page) Xilinx, Inc – Industry’s best 0.18 micron CMOS CPLD

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

XC2C512 Datasheet, PDF (3/14 Pages) Xilinx, Inc – Industry’s best 0.18 micron CMOS CPLD

◁

CoolRunner-II CPLD Family

Architecture Description

CoolRunner-II CPLD is a highly uniform family of fast, low

power CPLDs. The underlying architecture is a traditional

CPLD architecture combining macrocells into Function

Blocks (FBs) interconnected with a global routing matrix,

the Xilinx Advanced Interconnect Matrix (AIM). The Func-

tion Blocks use a Programmable Logic Array (PLA) config-

uration which allows all product tems to be routed and

shared among any of the macrocells of the FB. Design soft-

ware can efficiently synthesize and optimize logic that is

subsequently fit to the FBs and connected with the ability to

utilize a very high percentage of device resources. Design

changes are easily and automatically managed by the soft-

ware, which exploits the 100% routability of the Program-

mable Logic Array within each FB. This extremely robust

building block delivers the industryâs highest pinout reten-

tion, under very broad design conditions. The architecture

will be explained by expanding the detail as we discuss the

underlying Function Blocks, logic and interconnect.

The design software automatically manages these device

resources so that users can express their designs using

completely generic constructs without knowledge of these

architectural details. More advanced users can take advan-

tage of these details to more thoroughly understand the

softwareâs choices and direct its results.

Figure 1 shows the high-level architecture whereby Func-

tion Blocks attach to pins and interconnect to each other

within the internal interconnect matrix. Each FB contains 16

macrocells. The BSC path is the JTAG Boundary Scan Con-

trol path. The BSC and ISP block has the JTAG controller

and In-System Programming Circuits.

I/O Pin

Function

Block 1

MC1

MC2

BSC Path

Clock and Control Signals

Function

Block n

16 FB

MC1

MC2

I/O Pin

PLA

AIM

I/O Pin

JTAG

MC16

Fast Inputs

MC16

Fast Inputs

BSC and ISP

Figure 1: CoolRunner-II CPLD Architecture

I/O Pin

DS090_01_121201

DS090 (v1.7) October 2, 2003

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

▷