XC2C512 Datasheet, PDF (11/14 Pages) Xilinx, Inc – Industry’s best 0.18 micron CMOS CPLD

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CoolRunner-II CPLD Family
In System Programming
All CoolRunner-II CPLD parts are 1.8V in system program-
mable. This means they derive their programming voltage
and currents from the 1.8V V_CC (internal supply voltage)
pins on the part. The V_CCIO pins do not participate in this
operation, as they may assume another voltage ranging as
high as 3.3V down to 1.5V. A 1.8V V_CC is required to prop-
erly operate the internal state machines and charge pumps
that reside within the CPLD to do the nonvolatile program-
ming operations. The JTAG interface buffers are powered
by a dedicated power pin, V_CCAUX, which is independent of
all other supply pins. V_CCAUX must be connected. Xilinx
software is provided to deliver the bit-stream to the CPLD
and drive the appropriate IEEE 1532 protocol. To that end,
there is a set of IEEE 1532 commands that are supported in
the CoolRunner-II CPLD parts. Programming times are less
than one second for 32 to 256 macrocell parts. Program-
ming times are less than four seconds for 384 and 512 mac-
rocell parts. Programming of CoolRunner-II CPLDs is only
guaranteed when operating in the commercial temperature
and voltage ranges as defined in the device-specific data
sheets.
On-The-Fly Reconfiguration (OTF)
Xilinx ISE 5.2i supports OTF for CoolRunner-II CPLDs. This
permits programming a new nonvolatile pattern into the part
while another pattern is currently in use. OTF has the same
voltage and temperature specifications as system program-
ming. During pattern transition I/O pins are in high imped-
ancewith weak pullup to V_CCIO. Transition time typically
lasts between 50 and 100 µs, depending on density.
JTAG Instructions
Table 6 shows the commands available to users. These
same commands may be used by third party ATE products,
as well. The internal controllers can operate as fast as 66
MHz.
Table 6: JTAG Instructions
Code Instruction
Description
00000000 EXTEST Force boundary scan data onto
outputs
00000011 PRELOAD Latch macrocell data into
boundary scan cells
11111111 BYPASS Insert bypass register between
TDI and TDO
00000010 INTEST Force boundary scan data onto
inputs and feedbacks
Table 6: JTAG Instructions
Code Instruction
Description
00000001 IDCODE Read IDCODE
11111101 USERCODE Read USERCODE
11111100
HIGHZ
Force output into high
impedance state
11111010 CLAMP Latch present output state
Power-Up Characteristics
CoolRunner-II CPLD parts must operate under the
demands of both the high-speed and the portable market
places, therefore, they must support hot plugging for the
high-speed world and tolerate most any power sequence to
its various voltage pins. They must also not draw excessive
current during power-up initialization. To those ends, the
general behavior is summarized as follows:
1. I/O pins are disabled until the end of power-up.
2. As supply rises, configuration bits transfer from
nonvolatile memory to SRAM cells.
3. As power up completes, the outputs become as
configured (input, output, or I/O).
4. For specific configuration times and power up
requirements, see the device specific datasheet.
CoolRunner-II CPLD I/O pins are well behaved under all
operating conditions. During power-up, CoolRunner-II
devices employ internal circuitry which keeps the devices in
the quiescent state until the V_CCINT supply voltage is at a
safe level (approximately 1.3V). In the quiescent state,
JTAG pins are disabled, and all device outputs are disabled
with the pins weakly pulled high, as shown in Table 7. When
the supply voltage reaches a safe level, all user registers
become initialized, and the device is immediately available
for operation, as shown in Figure 12. Best results are
obtained with a smooth V_CC rise in less that 4 ms
If the device is in the erased state (before any user pattern
is programmed), the device outputs remain disabled with a
weak pull-up. The JTAG pins are enabled to allow the
device to be programmed at any time. All devices are
shipped in the erased state from the factory.
If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
JTAG pins are enabled to allow device erasure or
boundary-scan tests at any time.
DS090 (v1.7) October 2, 2003
www.xilinx.com
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Preliminary Product Specification
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