XC2C512 Datasheet, PDF (6/14 Pages) Xilinx, Inc – Industry’s best 0.18 micron CMOS CPLD

CoolRunner-II CPLD Family
R
pins.However, if VREF pin placement is not done properly,
additional VREF pins may be required, resulting in a loss of
potential I/O pins or board re-work. See XAPP 399 for
details regarding VREF pins and their placement.
V_REF has pin-range requirements that must be observed.
The Xilinx software aids designers in remaining within the
proper pin range.
To AIM
To Macrocell
Fast Input
Hysteresis
Available on 128 Macrocell Devices and Larger
VREF
Global termination
Pullup/Bus-Hold
Enabled
CTE
PTB
GTS[0:3]
4
CGND
Open Drain
Disabled
VCCIO
From Macrocell
Figure 4: CoolRunner-II CPLD I/O Block Diagram
DS090_04_121201
Table 4 summarizes the single ended I/O standard support
and shows which standards require V_REF values and board
termination. V_REF detail is given in specific data sheets.
Table 4: CoolRunner-II CPLD I/O Standard Summary
I/O Standard
LVTTL
V_CCIO
3.3
Input
V_REF
N/A
Board Termination
Voltage (V_TT)
N/A
LVCMOS33
3.3
N/A
N/A
LVCMOS25
2.5
N/A
N/A
LVCMOS18
1.8
N/A
N/A
1.5V I/O
1.5
N/A
N/A
HSTL-1
1.5 0.75
0.75
SSTL2-1
2.5 1.25
1.25
SSTL3-1
3.3
1.5
1.5
Output Banking
CPLDs are widely used as voltage interface translators. To
that end, the output pins are grouped in large banks. The
smallest parts are not banked, so all signals will have the
same output swing for 32 and 64 macrocell parts. The
medium parts (128 and 256 macrocell) support two output
banks. With two, the outputs will switch to one of two
selected output voltage levels, unless both banks are set to
the same voltage. The larger parts (384 and 512 macrocell)
support four output banks split evenly. They can support
groupings of one, two, three or four separate output voltage
levels. This kind of flexibility permits easy interfacing to
3.3V, 2.5V, 1.8V, and 1.5V in a single part.
DataGATE
Low power is the hallmark of CMOS technology. Other
CPLD families use a sense amplifier approach to creating
product terms, which always has a residual current compo-
nent being drawn. This residual current can be several hun-
dred milliamps, making them unusable in portable systems.
CoolRunner-II CPLDs use standard CMOS methods to cre-
ate the CPLD architecture and deliver the corresponding
low current consumption, without doing any special tricks.
However, sometimes designers would like to reduce their
system current even more by selectively disabling circuitry
not being used.
The patented DataGATE technology was developed to per-
mit a straightforward approach to additional power reduc-
tion. Each I/O pin has a series switch that can block the
arrival of free running signals that are not of interest. Sig-
nals that serve no use may increase power consumption,
and can be disabled. Users are free to do their design, then
choose sections to participate in the DataGATE function.
DataGATE is a logic function that drives an assertion rail
threaded through the medium and high-density
CoolRunner-II CPLD parts. Designers can select inputs to
be blocked under the control of the DataGATE function,
effectively blocking controlled switching signals so they do
not drive internal chip capacitances. Output signals that do
not switch, are held by the bus hold feature. Any set of input
pins can be chosen to participate in the DataGATE function.
Figure 5 shows the familiar CMOS I_CC versus switching fre-
quency graph. With DataGATE, designers can approach
zero power, should they choose to, in their designs
Figure 6 shows how DataGATE basically works. One I/O
pin drives the DataGATE Assertion Rail. It can have any
desired logic function on it. It can be as simple as mapping
an input pin to the DataGATE function or as complex as a
counter or state machine output driving the DataGATE I/O
6
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DS090 (v1.7) October 2, 2003
1-800-255-7778
Preliminary Product Specification