XC2C512 Datasheet, PDF (1/14 Pages) Xilinx, Inc – Industry’s best 0.18 micron CMOS CPLD

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CoolRunner-II CPLD Family
DS090 (v1.7) October 2, 2003
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Features
• Optimized for 1.8V systems
- Industry’s fastest low power CPLD
- Static Icc of less than 100 microamps at all times
- Densities from 32 to 512 macrocells
• Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation — 1.5V to 3.3V
• Advanced system features
- Fastest in system programming
· 1.8V ISP using IEEE 1532 (JTAG) interface
- On-The-Fly Reconfiguration (OTF)
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt trigger input (per pin)
- Unsurpassed low power management
- FZP 100% CMOS product term generation
- DataGATE external signal control
- Flexible clocking modes
· Optional DualEDGE triggered registers
· Clock divider (÷ 2,4,6,8,10,12,14,16)
· CoolCLOCK
- Global signal options with macrocell control
· Multiple global clocks with phase selection per
macrocell
· Multiple global output enables
· Global set/reset
- Abundant product term clocks, output enables and
set/resets
- Efficient control term clocks, output enables and
set/resets for each macrocell and shared across
function blocks
- Advanced design security
- Open-drain output option for Wired-OR and LED
drive
- Optional bus-hold or weak pullup on select I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels on all parts
· SSTL2-1,SSTL3-1, and HSTL-1 on 128 macro-
cell and denser devices
- PLA architecture
· Superior pinout retention
· 100% product term routability across function
block
- Hot pluggable
- Wide package availability including fine pitch:
· Chip Scale Package (CSP) BGA, Fine Line BGA,
TQFP, PQFP, VQFP, and PLCC packages
- Design entry/verification using Xilinx and industry
standard CAE tools
- Free software support for all densities using Xilinx
WebPACK™ or WebFITTER™ tools
- Industry leading nonvolatile 0.18 micron CMOS
process
- Guaranteed 1,000 program/erase cycles
- Guaranteed 20 year data retention
Family Overview
Xilinx CoolRunner™-II CPLDs deliver the high speed and
ease of use associated with the XC9500/XL/XV CPLD fam-
ily with the extremely low power versatility of the XPLA3™
family in a single CPLD. This means that the exact same
parts can be used for high-speed data communications/
computing systems and leading edge portable products,
with the added benefit of In System Programming. Low
power consumption and high-speed operation are com-
bined into a single family that is easy to use and cost effec-
tive. Xilinx patented Fast Zero Power™ (FZP) architecture
inherently delivers very low power performance without the
need for any special design measures. Clocking techniques
and other power saving features extend the users’ power
budget. The design features are supported starting with Xil-
inx ISE 4.1i, WebFITTER, and ISE WebPACK. Additional
details can be found in Further Reading, page 13.
Table 1 shows the macrocell capacity and key timing
parameters for the CoolRunner-II CPLD family.
Table 1: CoolRunner-II CPLD Family Parameters
XC2C32
XC2C64
XC2C128
XC2C256
XC2C384
XC2C512
Macrocells
32
64
128
256
384
512
Max I/O
33
64
100
184
240
270
T_PD (ns)
3.5
4.0
4.5
5.0
5.5
6.0
T_SU (ns)
1.7
2.0
2.1
2.2
2.3
2.4
T_CO (ns)
2.8
3.0
3.4
3.8
4.2
4.6
F_SYSTEM1 (MHz)
333
270
263
238
217
217
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DS090 (v1.7) October 2, 2003
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Preliminary Product Specification
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