XC2C512 Datasheet, PDF(10/14 Page) Xilinx, Inc – Industry’s best 0.18 micron CMOS CPLD

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XC2C512 Datasheet, PDF (10/14 Pages) Xilinx, Inc – Industry’s best 0.18 micron CMOS CPLD

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CoolRunner-II CPLD Family

TIN

TFIN

TGCK

TGSR

TGTS

THYS

TLOGI1

TLOGI2

TCT

TPDI

D/T TCOI

TSUI THI

TECSU

TECHO

CE TAOI

S/R

TOUT

TOEM

TEN

TSLEW

THYS

Figure 11: CoolRunner-II CPLD Timing Model

DS090_11_12

Table 5: Timing Parameter Definitions

Symbol

Parameter

Buffer Delays

TlN

Input Buffer Delay

TFIN

Fast data register input delay

TGCK

Global clock (GCK) buffer delay

TGSR

Global set/reset (GSR) buffer delay

TGTS

Global output enable (GTS) buffer delay

TOUT

Output buffer delay

TEN

Output buffer enable/disable delay

TSLEW

Output buffer slew rate control delay

P-term Delays

TCT

TLOGI1

TLOGI2

Control Term delay (single PT or FB-CT)

Single P-term logic delay

Multiple P-term logic delay adder

Table 5: Timing Parameter Definitions (Continued)

Symbol

Parameter

Macrocell Delays

TPDI

Macro cell input to output valid

TSUI

Macro register setup before clock

THI

Macro register hold after clock

TECSU

Macro register enable clock setup time

TECHO

Macro register enable clock hold time

TCOI

Macro register clock to output valid

TAOI

Macro register set/reset to output valid

THYS

Hysteresis selection delay adder

Feedback Delays

TOEM

Feedback delay

Macrocell to Global OE delay

www.xilinx.com

DS090 (v1.7) October 2, 2003

1-800-255-7778

Preliminary Product Specification

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