XC2C512 Datasheet, PDF (8/14 Pages) Xilinx, Inc – Industry’s best 0.18 micron CMOS CPLD

CoolRunner-II CPLD Family
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Global Signals
Global signals, clocks (GCK), sets/resets (GSR) and output
enables (GTS), are designed to strongly resemble each
other. This approach enables design software to make the
best utilization of their capabilities. Each global capability is
supplemented by a corresponding product term version.
Figure 7 shows the common structure of the global signal
trees. The pin input is buffered, then drives multiple internal
global signal traces to deliver low skew and reduce loading
delays. The DataGATE assertion rail is also a global signal.
DS090_07_101001
Figure 7: Global Clocks (GCK), Sets/Resets (GSR) and
Output Enables (GTS)
Additional Clock Options: Division,
DualEDGE, and CoolCLOCK
Division
Circuitry has been included in the CoolRunner-II CPLD
architecture to divide one externally supplied global clock
by standard values. Division by 2,4,6,8,10, 12, 14 and 16
are the options (see Figure 8). This capability is supplied on
the GCK2 pin. The resulting clock produced will be 50%
duty cycle for all possible divisions. Note that a Synchro-
nous Reset (CDRST) is included to guarantee no runt
clocks can get through to the global clock nets. Note that
again, the signal is buffered and driven to multiple traces
with minimal loading and skew.
DualEDGE
Each macrocell has the ability to double its input clock
switching frequency. Figure 9 shows the macrocell flip-flop
with the DualEDGE option (doubled clock) at each macro-
cell. The source to double can be a control term clock, a
product term clock or one of the available global clocks. The
ability to switch on both clock edges is vital for a number of
synchronous memory interface applications as well as cer-
tain double data rate I/O applications.
CoolCLOCK
In addition to the DualEDGE flip-flop, additional power sav-
ings can be had by combining the clock division circuitry
with the DualEDGE circuitry. This capability is called Cool-
CLOCK and is designed to reduce clocking power within the
CPLD. Because the clock net can be an appreciable power
drain, the clock power can be reduced by driving the net at
half frequency, then doubling the clock rate using
DualEDGE triggering at the macrocells. Figure 10 shows
how CoolCLOCK is created by internal clock cascading with
the divider and DualEDGE flip-flop working together.
GCK2
÷2
÷4
÷6
Clock ^÷8
In
÷10
÷12
÷14
÷16
CDRST
CDRST
DS090_08_121201
Figure 8: Clock Division Circuitry for GCK2
8
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DS090 (v1.7) October 2, 2003
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Preliminary Product Specification