XC2C512 Datasheet, PDF (7/14 Pages) Xilinx, Inc – Industry’s best 0.18 micron CMOS CPLD

R
CoolRunner-II CPLD Family
pin through a macrocell. When the DataGATE rail is
asserted high, any pass transistor switch attached to it is
blocked. Note that each pin has the ability to attach to the
AIM through a DataGATE pass transistor, and thus be
blocked. A latch automatically captures the state of the pin
when it becomes blocked. The DataGATE Assertion Rail
threads throughout all possible I/Os, so each can participate
if chosen. Note that one macrocell is singled out to drive the
rail, and that macrocell is exposed to the outside world
through a pin, for inspection. If DataGATE is not needed,
this pin is an ordinary I/O.
ICC
0
Frequency
DS090_05_101001
Figure 5: CMOS I_CC vs. Switching Frequency Curve
DataGATE Assertion Rail
MC1
MC2
MC1
MC2
To AIM
Latch
PLA
Latch
To AIM
MC16
MC1
MC2
AIM
PLA
To AIM
Latch
MC16
MC1
MC2
PLA
Latch
To AIM
MC16
PLA
To AIM
Latch
MC16
Figure 6: DataGATE Architecture (output drivers not shown)
DS090_06_111201
DS090 (v1.7) October 2, 2003
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Preliminary Product Specification
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