XC2C512 Datasheet, PDF (12/14 Pages) Xilinx, Inc – Industry’s best 0.18 micron CMOS CPLD

CoolRunner-II CPLD Family
R
V_CCINT
3(¹⁽_T.T8^._yy3pVpV))
0V
No
Power
Quiescent
State
User Operation
Quiescent No
State Power
Initialization of User Registers
x382_10
Figure 12: Device Behavior During Power Up
Table 7: I/O Power-Up Characteristics
Device Circuitry
Quiescent State
IOB Bus-Hold/Weak Pullup
Weak Pull-up
Device Outputs
Disabled
Device Inputs and Clocks
Disabled
Function Block
Disabled
JTAG Controller
Disabled
Erased Device Operation
Weak Pull-up
Disabled
Disabled
Disabled
Enabled
Valid User Operation
Bus-Hold/Weak Pullup
As Configured
As Configured
As Configured
Enabled
I/O Banking
CoolRunner-II CPLD 32 and 64 macrocell parts support a
single V_CCIO rail that can range from 3.3V down to 1.5V
operation. Two V_CCIO rails are supported on the 128 and
256 macrocell parts where outputs on each rail can inde-
pendently range from 3.3V down to 1.5V operation. Four
V_CCIO rails are supported on the 384 and 512 macrocell
parts with each rail independently supporting any voltage
between 3.3V and 1.5V. The V_CC (internal supply voltage)
for a CoolRunner-II CPLD must be maintained within 1.8V
±5% for correct speed operation and proper in system pro-
gramming.
Mixed Voltage, Power Sequencing, and
Hot Plugging
As mentioned in I/O Banking, CoolRunner-II CPLD parts
support mixed voltage I/O signals where signals within the
same bank can range from 3.3V down to 1.5V. The power
applied to the V_CCIO and V_CC pins can occur in any order
and the CoolRunner-II CPLD will not be damaged. For best
results, it is recommended that V_CCINT be applied before
V_CCIO. CoolRunner-II CPLDs can reside on boards where
the board is inserted into a “live” connector (hot plugged)
and the parts will be well-behaved as if powering up in a
standard way.
Development System Support
Xilinx CoolRunner-II CPLDs are supported by all configura-
tions of Xilinx standard release development software as
well as the freely available WebFITTER and ISE WebPACK
software available from www.xilinx.com. Third party devel-
opment tools include synthesis tools from Cadence, Exem-
plar, Mentor Graphics, Synplicity, and Synopsys.
ATE Support
Third party ATE development support is available for both
programming and board/chip level testing. Vendors provid-
ing this support include Agilent, GenRad, and Teradyne.
Other third party providers are expected to deliver solutions
in the future.
12
www.xilinx.com
DS090 (v1.7) October 2, 2003
1-800-255-7778
Preliminary Product Specification