DS789 Datasheet, PDF (9/12 Pages) Xilinx, Inc – Connects as a 32-bit slave on AXI4-Lite Interface

LogiCORE IP AXI System ACE Interface Controller (axi_sysace) (v1.01.a)
AXI System ACE Interface Controller Parameter-Port Dependencies
The dependencies between the AXI System ACE Interface Controller design parameters and I/O signals are
described in Table 5. In addition, when certain features are parameterized out of the design, the related logic will no
longer be a part of the design. The unused input signals and related output signals are set to a specified value.
Table 5: AXI System ACE Interface Controller Parameter-Port Dependencies
Generic
or Port
Parameter
Affects Depends
Relationship Description
Design Parameters
G4 C_S_AXI_ADDR_WIDTH
P3,P13
-
Width of the AXI Address Bus
G5 C_S_AXI_DATA_WIDTH
P6,P7,P16
-
Width of the AXI Data Bus
I/O Signals
P3 S_AXI_AWADDR[C_S_AXI_ADDR_WIDTH-1:0]
-
G4
Width varies with the width of the
AXI Address Bus width
P6 S_AXI_WDATA[C_S_AXI_DATA_WIDTH-1:0]
-
G5
Width varies with the AXI data bus
width
P7 S_AXI_WSTB[C_S_AXI_DATA_WIDTH/8-1:0]
-
G5
Width varies with the width of the
AXI Data Bus width
P13 S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH-1:0]
-
G4
Width varies with the width of the
AXI Address Bus width
P16 S_AXI_RDATA[C_S_AXI_DATA_WIDTH-1:0]
-
G5
Width varies with the width of the
AXI Data Bus width
Design Implementation
Target Technology
The intended target technology is the Artix ™-7, Virtex ®-7, Kintex ™-7, Virtex-6 and Spartan®-6 FPGAs.
Device Utilization and Performance Benchmarks
Core Performance
Since the AXI System ACE Controller will be used with other design modules in the FPGA, the utilization and
timing numbers reported in this section are just estimates. When the AXI System ACE Interface Controller is
combined with other designs in the system, the utilization of FPGA resources and timing will vary from the results
reported here.
The AXI System ACE Interface Controller benchmarks are shown in Table 6 through Table 10.
Table 6: Performance and Resource Utilization Benchmarks for Artix-7 FPGAs (XC7A355TDIE)
Parameter Values
C_MEM_WIDTH
C_BASEADDR
C_HIGHADDR
8
0x30000000
0x3FFFFFFF
16
0x30000000
0x3FFFFFFF
Device Resources
Slices
Slice
Flip-Flops
LUTs
49 90
81
53 114
75
Performance
F_max
(in MHz)
247.709
211.954
DS789 June 22, 2011
www.xilinx.com
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Product Specification