DS789 Datasheet, PDF (4/12 Pages) Xilinx, Inc – Connects as a 32-bit slave on AXI4-Lite Interface

X-Ref Target - Figure 2
LogiCORE IP AXI System ACE Interface Controller (axi_sysace) (v1.01.a)
Bus2IP_RdCE
Bus2IP_WrCE
Mem_A
Mem_DQ_O
Mem_DQ_T
Mem_DQ_I
IP2Bus_RdAck
IP2Bus_WrAck
S_AXI_ACLK
SYNC_2_CLKS
SysACE_MPA
SysACE_MPD_O
SysACE_MPD_T
SysACE_MPD_I
3-State Buffer
Added in
System
Generation
SysACE_Clk
valid_mem_t
MEM_STATE_MACHINE
SysACE_CEN
SysACE_OEN
SysACE_WEN
SysACE_Clk
Figure 2: System ACE Interface Controller Diagram
The AXI System ACE Interface Controller core does not contain any internal registers or addressable memory
space; therefore, the mapping of the AXI address bus is one-to-one with the System ACE address bus
(SysACE_MPA) as shown in Table 1.
Table 1: AXI Address Bus to System ACE Address Bus Mapping (Done in IP Core)
AXI Address Bus
System ACE Address Bus
AXI_ABus[6 : 0]
SysACE_MPA[6 : 0]
The Xilinx System ACE Compact Flash chip and AXI are both little-endian, therefore the AXI System ACE Interface
Controller has one-to-one mapping as shown in Table 2.
Table 2: AXI Data Bus to System ACE Data Bus Mapping (Done in IP Core)
AXI Data Bus
System ACE Data Bus
AXI_DBus[15 : 8]
SysACE_MPD[15 : 8]
AXI_DBus[7 : 0]
SysACE_MPD[7 : 0]
Clocking - SYNC_2_CLKS Module
The controller state machine runs on the SysACE_Clk. The IPIC signals indicating the start of a transaction are
synchronized to the System ACE clock and used to start the state machine. All address, data and control signals that
are output to the System ACE Compact Flash chip are synchronized to the SysACE_Clk and registered in the
FPGA IO registers using SysACE_Clk to ensure a clean interface between this chip and the FPGA. Data from the
System ACE Compact Flash chip is also registered in FPGA IO registers using SysACE_Clk. It is then synchronized
to the S_AXI_ACLK for transmission on the bus. The frequency of the SysACE_Clk must be less than the frequency
of the S_AXI_ACLK.
DS789 June 22, 2011
www.xilinx.com
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Product Specification