DS789 Datasheet, PDF (11/12 Pages) Xilinx, Inc – Connects as a 32-bit slave on AXI4-Lite Interface

LogiCORE IP AXI System ACE Interface Controller (axi_sysace) (v1.01.a)
The target FPGA was then filled with logic to drive the LUT and block RAM utilization to approximately 70% and
the I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target
FPGA, the resulting target FMax numbers are shown in Table 11.
Table 11: AXI SYSACE Controller Core System Performance
Target FPGA
Artix-7
Target f_MAX (MHz)
110
Virtex-7
180
Kintex-7
180
Virtex-6
180
Spartan-6
110
The target fMAX is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE® Design Suite Embedded
Edition software under the terms of the Xilinx End User License. The core is generated using the Xilinx ISE
Embedded Edition software (EDK).
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page.
For information on pricing and availability of other Xilinx LogiCORE modules and software, please contact your
local Xilinx sales representative.
Reference Documents
The following documents contain reference information important to understanding the AXI SYSACE Controller
design:
• AMBA AXI Protocol Version: 2.0 Specification (ARM® IHI 0022C)
• WP151, System ACE Configuration Solution for Xilinx FPGAs
• DS080, System ACE Compact Flash Solution
• DS768, AXI Interconnect IP Data Sheet
List of Acronyms
Acronym
ACE
AMBA
ARM
AXI
DUT
FF
FPGA
IO
Meaning
Advanced Configuration Environment
Advanced Microcontroller Bus Architecture
Advanced RISC Machine
Advanced eXtensible Interface
Device Under Test
Flip-Flop
Field Programmable Gate Array
Input/Output
DS789 June 22, 2011
www.xilinx.com
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Product Specification