DS789 Datasheet, PDF (10/12 Pages) Xilinx, Inc – Connects as a 32-bit slave on AXI4-Lite Interface

LogiCORE IP AXI System ACE Interface Controller (axi_sysace) (v1.01.a)
Table 7: Performance and Resource Utilization Benchmarks for Virtex-7 FPGAs (XC7V855T-FFG1157-3)
Parameter Values
Device Resources
Performance
C_MEM_WIDTH
C_BASEADDR
C_HIGHADDR Slices
Slice
Flip-Flops
LUTs F_max (in MHz)
8
0x30000000
0x3FFFFFFF
62
114
74
202.102
16
0x30000000
0x3FFFFFFF
62
114
74
202.102
Table 8: Performance and Resource Utilization Benchmarks for Kintex-7 FPGAs (XC7K410T-FFG676-3)
Parameter Values
Device Resources
Performance
C_MEM_WIDTH
C_BASEADDR
C_HIGHADDR Slices
Slice
Flip-Flops
LUTs F_max(in MHz)
8
0x30000000
0x3FFFFFFF
54
90
81
211.282
16
0x30000000
0x3FFFFFFF
60
114
75
207.297
Table 9: Performance and Resource Utilization Benchmarks for Virtex-6 FPGAs (XC6VLX195T-1-FF1156)
Parameter Values
Device Resources
Performance
C_MEM_WIDTH
C_BASEADDR
C_HIGHADDR Slices
Slice
Flip-Flops
LUTs
F_max
(in MHz)
8
0x30000000
0x3FFFFFFF
44
136
64
243.962
16
0x30000000
0x3FFFFFFF
46
160
75
235.46
Table 10: Performance and Resource Utilization Benchmarks for Spartan-6 FPGAs (XC6SLX45-2-FGG484)
Parameter Values
Device Resources
Performance
C_MEM_WIDTH
C_BASEADDR
C_HIGHADDR Slices
Slice
Flip-Flops
LUTs
F_max
(in MHz)
8
0x30000000
0x3FFFFFFF
58
183
72
156.986
16
0x30000000
0x3FFFFFFF
70
207
67
161.734
System Performance
To measure the system performance (Fmax) of this core, this core was added to a Virtex-6 FPGA system, and a
Spartan-6 FPGA system as the Device Under Test (DUT).
Because the AXI SYSACE Controller core will be used with other design modules in the FPGA, the utilization and
timing numbers reported in this section are estimates only. When this core is combined with other designs in the
system, the utilization of FPGA resources and timing of the core design will vary from the results reported.
DS789 June 22, 2011
www.xilinx.com
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Product Specification