DS789 Datasheet, PDF (3/12 Pages) Xilinx, Inc – Connects as a 32-bit slave on AXI4-Lite Interface

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LogiCORE IP AXI System ACE Interface Controller (axi_sysace) (v1.01.a)
AXI System ACE Interface Controller
AXI4-Lite
Interface
Module
IPIC
Bus2IP_CS
Bus2IP_RNW
Bus2IP_Addr(0:31)
Bus2IP_Data(0:31)
Bus2IP_BE(0:3)
Bus2IP_RdCE
Bus2IP_WrCE
Bus_Clk
Bus_reset
IP2Bus_Data(31:0)
IP2Bus_errack
IP2Bus_RdAck
IP2Bus_WrAck
SysACE_Clk ³
SysACE_CEN
SysACE_OEN
SysACE_WEN
SysACE_MPA
System ACE SysACE_MPD¹
Interface
Controller
Xilinx
System ACE
Controller
Device
Compact
Flash
chip
SysACE_IRQ²
SysACE_MPIRQ
Notes:
1. SysACE_MPD is formed in the IOB from SysACE_MPD_I, SysACE_MPD_0, and SysACE_MPD_T.
2. SysACE_IRQ should be connected to the interrupt input of the processor.
3. SysACE_Clk should be connected to a global clock buffer by the user.
Figure 1: AXI System ACE Interface Controller Block Diagram
AXI4-Lite Interface Module
AXI4-Lite Interface Module provides an interface between AXI System ACE Interface Controller and the AXI. The
AXI4-Lite Interface Module implements the basic functionality of an AXI slave and does the necessary protocol and
timing translation between the AXI and the IPIC interface. The AXI4-Lite Interface Module supports only single
beat transactions.
System ACE Interface Controller
The System ACE interface controller contains a controller state machine and logic to synchronize signals across the
S_AXI_ACLK and SysACE_Clk domains as shown in Figure 2.
DS789 June 22, 2011
www.xilinx.com
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Product Specification