DS789 Datasheet, PDF (5/12 Pages) Xilinx, Inc – Connects as a 32-bit slave on AXI4-Lite Interface

LogiCORE IP AXI System ACE Interface Controller (axi_sysace) (v1.01.a)
Note that the address and data (if a write transaction) from the AXI will stay stable during the entire bus transaction
and therefore would not have to be synchronized and output using the SysACE_Clk. This was done to provide a
robust design, however, if the overall FPGA design is limited on resources, these synchronization registers could
possibly be removed. The user is cautioned to analyze timing before removing these registers.
Also note that this core does not instantiate a global clock buffer for SysACE_Clk. This is left for the user to
instantiate based on the resource requirements of their system.
System ACE Control State Machine - MEM_STATE_MACHINE Module
The state machine in the System ACE Interface controller performs the specified transaction to the MPU interface of
the System ACE Compact Flash chip and is shown in Figure 3. This state machine is clocked by SysACE_Clk and
therefore outputs all System ACE control signals synchronous to this clock. The input control signals from the
AXI4-Lite Interface Module have been synchronized to the SysACE_Clk in the sync_2_clocks module.
X-Ref Target - Figure 3
IDLE
idle_rdce_re | sync_wrce_re
ASSERT_CEN
sync_rdce
sync_wrce
IDLE
ASSERT_OEN
ASSERT_WEN
ASSERT_DONE
NEGATE_CEN
Figure 3: System ACE Interface Control State Machine
DS789 June 22, 2011
www.xilinx.com
5
Product Specification