DS789 Datasheet, PDF (6/12 Pages) Xilinx, Inc – Connects as a 32-bit slave on AXI4-Lite Interface

LogiCORE IP AXI System ACE Interface Controller (axi_sysace) (v1.01.a)
AXI System ACE Interface Controller I/O Signals
The I/O signals for the AXI System ACE Interface Controller are listed and described in Table 3.
Table 3: AXI System ACE Interface Controller I/O Signals
Port
Signal Name
Interface
I/O
Initial
State
Description
System Signals
P1 S_AXI_ACLK
AXI
I
- AXI clock
P2 S_AXI_ARESETn
AXI
I
- AXI reset, active low
AXI Write Address Channel Signals
P3 S_AXI_AWADDR
[C_S_AXI_ADDR_WIDTH - 1:0]
AXI
I
- AXI Write address. The write address bus
gives the address of the write transaction.
P4 S_AXI_AWVALID
AXI
I
- Write address valid. This signal indicates
that valid write address is available.
P5 S_AXI_AWREADY
AXI
O 0x0 Write address ready. This signal indicates
that the slave is ready to accept an
address.
AXI Write Data Channel Signals
P6 S_AXI_WDATA
[C_S_AXI_DATA_WIDTH - 1:0]
AXI
I
- Write Data
P7 S_AXI_WSTB
[C_S_AXI_DATA_WIDTH/8-1:0]
AXI
I
- Write strobes. This signal indicates which
byte lanes to update in memory
P8 S_AXI_WVALID
AXI
I
- Write valid. This signal indicates that valid
write data and strobes are available.
P9 S_AXI_WREADY
AXI
O 1’b0 Write ready. This signal indicates that the
slave can accept the write data.
AXI Write Response Channel Signals
P10 S_AXI_BRESP[1:0]
AXI
O 0x0 Write response. This
signal indicates the status of the write
transaction.
“00“ - OKAY
“10“ - SLVERR
P11 S_AXI_BVALID
AXI
O 1’b0 Write response valid. This signal indicates
that a valid write response is available.
P12 S_AXI_BREADY
AXI
I
- Response ready. This signal indicates that
the master can accept the response
information.
AXI Read Address Channel Signals
P13 S_AXI_ARADDR
[C_S_AXI_ADDR_WIDTH-1:0]
AXI
I
- Read Address. The read address bus
gives the address of a read transaction.
P14 S_AXI_ARVALID
AXI
I
- Read address valid. This signal indicates,
when HIGH, that the read address is valid
and will remain stable until the address
acknowledgement signal,
S_AXI_AREADY, is high.
P15 S_AXI_ARREADY
AXI
O 1’b1 Read address ready. This signal indicates
that the slave is ready to accept an
address
DS789 June 22, 2011
www.xilinx.com
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Product Specification