DS789 Datasheet, PDF (7/12 Pages) Xilinx, Inc – Connects as a 32-bit slave on AXI4-Lite Interface

LogiCORE IP AXI System ACE Interface Controller (axi_sysace) (v1.01.a)
Table 3: AXI System ACE Interface Controller I/O Signals (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
Description
AXI Read Data Channel Signals
P16 S_AXI_RDATA[C_S_AXI_DATA_WIDTH-
AXI
1:0]
O 0x0 Read Data
P17 S_AXI_RRESP[1:0]
AXI
O 0x0 Read response. This signal indicates the
status of the read transfer:
“00” - OKAY
“10” - SLVERR
P18 S_AXI_RVALID
AXI
O 1’b0 Read valid. This signal indicates that the
required read data is available and the
read transfer can complete.
P19 S_AXI_RREADY
AXI
I
- Read ready. This signal indicates that the
master can accept the read data and
response information.
P20 SysACE_Clk⁽¹⁾
Signals
System
I
Ace Core
- System ACE Clock
P21 SysACE_MPIRQ
System
I
Ace Core
- System ACE Active high Interrupt Input
P22 SysACE_CEN
System O
Ace Core
1 System ACE Chip Enable
P23 SysACE_OEN
System O
Ace Core
1 System ACE Output Enable
P24 SysACE_WEN
System O
Ace Core
1 System ACE Write Enable
P25 SysACE_MPA[6 : 0]
System O
Ace Core
0 System ACE Address
P26 SysACE_MPD_I[C_MEM_WIDTH-1 : 0] System
I
Ace Core
- System ACE Data Input
P27 SysACE_MPD_O[C_MEM_WIDTH-1 : 0] System O
Ace Core
0 System ACE Data Output
P28 SysACE_MPD_T[C_MEM_WIDTH-1 : 0] System O
Ace Core
1 System ACE Data Output enable
P29 SysACE_IRQ⁽²⁾
System O
Ace Core
0 System ACE Active High Interrupt Output
Note:
1. S_AXI_ACLK frequency must be greater than or equal to SysACE_Clk Frequency.
2. This interrupt output is just a pass-through of the System ACE interrupt (SysACE_MPIRQ) and should be connected to an
interrupt controller or directly to the processor’s interrupt input.
DS789 June 22, 2011
www.xilinx.com
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Product Specification