DS789 Datasheet, PDF (8/12 Pages) Xilinx, Inc – Connects as a 32-bit slave on AXI4-Lite Interface

LogiCORE IP AXI System ACE Interface Controller (axi_sysace) (v1.01.a)
AXI System ACE Interface Controller Design Parameters
To allow the designer to obtain a AXI SYSACE core that is uniquely tailored for the designer’s system, certain
features can be parameterized. Some of these parameters control the interface to the AXI interface module while
others provide information to minimize resource utilization. The features that can be parameterized in the AXI
SYSACE are shown in Table 4.
In addition to the parameters listed in this table, there are also parameters that are inferred for each AXI interface in
the EDK tools. Through the design, these EDK-inferred parameters control the behavior of the AXI Interconnect.
For a complete list of the interconnect settings related to the AXI interface, see DS768, AXI Interconnect IP Data Sheet.
Table 4: AXI System ACE Interface Controller Parameters
Generic
Feature/Description
Parameter Name Allowable Values Default Value VHDL Type
System Parameter
G1 Target FPGA family
C_FAMILY
virtex6, spartan6
virtex6
string
AXI Parameters
G2 AXI System ACE Base Address C_BASEADDR
Valid Address^[1]
G3 AXI System ACE High Address C_HIGHADDR
Valid Address^[1]
0xFFFFFFFF^[1]
0x00000000^[1]
std_logic_
vector
std_logic_
vector
G4 AXI address bus width
C_S_AXI_ADDR_ 32
WIDTH
32
integer
G5 AXI data bus width
C_S_AXI_DATA_
32
WIDTH
32
integer
System ACE Parameters
G6 System ACE MPU Data Bus
Access Mode^[2]
C_MEM_WIDTH
8, 16
16
integer
Note:
1. The range specified by C_BASEADDR and C_HIGHADDR must be sized and aligned to some power of 2, 2ⁿ. Then, the n least
significant bits of C_BASEADDR is zero. This range needs to encompass the addresses needed by the AXI SYSACE registers
2. See Xilinx DS080, System ACE Compact Flash Solution, for more information.
Allowable Parameter Combinations
The address-range size of the AXI System ACE Interface Controller must be a power of 2. If the desired
address-range size is represented by 2ⁿ, then the n least significant bits of the base address must be 0.
C_BASEADDR and C_HIGHADDR must specify an address range whose size is at least 0x80 bytes, to cover the
addressable registers and data buffer available in the Xilinx System Ace Compact Flash chip.
DS789 June 22, 2011
www.xilinx.com
8
Product Specification