DS726 Datasheet, PDF (9/12 Pages) Xilinx, Inc – OPB to PLBV46 Bridge

OPB to PLBV46 Bridge (v1.01a)
Parameter-Port Dependencies
N/A
Device Utilization and Performance Benchmarks
Core Performance
Because the opb_plbv46_bridge is a module that will be used with other design pieces in the FPGA, the
resource utilization and timing numbers reported in this section are estimates only. When the
opb_plbv46_bridge is combined with other pieces of the FPGA design, the utilization of FPGA
resources and timing of the design will vary from the results reported here.
For Spartan®-3E FPGA systems the performance of the PLBv46 interface in 1:2 clock ratio mode should
meet or exceed 90 MHz. Similarly, for Virtex®-5 FPGA systems the performance should meet or exceed
120 MHz. In some system configurations (in either 1:1 or 1:2 clock ratio mode) the OPB bus could be the
limiting factor thus preventing the PLBv46 interface from reaching full speed. Use of the core in 1:1
clock ratio mode is offered only as an option and no clock frequency performance numbers are
provided for it.
The plbv46_opb_bridge resource utilization benchmarks for an xc5vlx50-1-ff676 FPGA for a variety of
generic parameter combinations applied on top of a base parameter set are shown in Table 3.
Table 3: FPGA Resource Utilization Benchmarks
Parameter Values (For Example)
Device Resources
1
2³²
X
X
X
1
2 0x20000000 0x20000000
X
X
1
3 0x20000000 0x20000000 0x20000000
X
1
4 0x20000000 0x20000000 0x20000000 0x20000000 1
4
0x200
0x200
0x200
0x200
1
4
0x200
0x200
Notes: Generic parameters used:
1. C_MPLB_AWIDTH=32
2. C_MPLB_DWIDTH=32
3. C_MPLB_NATIVE_DWIDTH=32
4. C_FAMILY="virtex5"
0x200
0x200
2
10 414 571 346
10 408 567 314
10 408 559 298
10 408 564 367
10 368 496 320
20 380 517 305
DS726 April 24, 2009
www.xilinx.com
9
Product Specification