DS726 Datasheet, PDF (12/12 Pages) Xilinx, Inc – OPB to PLBV46 Bridge

OPB to PLBV46 Bridge (v1.01a)
The target FPGA was then filled with logic to drive the LUT and block RAM utilization to
approximately 70% and the I/O utilization to approximately 80%. Using the default tool options and
the slowest speed grade for the target FPGA, the resulting target F_MAX numbers are shown in Table 4.
Table 4: OPB to PLBv46 Bridge Core System Performance
Target FPGA
S3A700 -4
Target F_MAX (MHz)
90
V4FX60 -10
100
V5LXT50 -1
120
The target F_MAX is influenced by the exact system and is provided solely for guidance. It is not a
guaranteed value across all systems.
Reference Documents
The following documents contain reference information important to understanding the OPB to
PLBV46 Bridge design:
1. IBM CoreConnect 128-Bit Processor Local Bus: Architecture Specification
2. IBM CoreConnect 64-Bit On-Chip Peripheral Bus: Architecture Specifications
3. Xilinx PLBv46 Interconnect and Interfaces Simplifications and Feature Subset Specification
Revision History
The following table shows the revision history for this document.
Date
6/11/07
10/3/07
12/13/07
9/17/08
04/24/09
Version
1.0
1.1
1.2
1.3
1.4
Revision
Initial Xilinx release.
Added FMax Margin System Performance section.
Added Virtex-II Pro FPGA support.
Updated for EDK11.1 release; removed Virtex-II support.
Replaced references to supported device families and tool name(s) with hyperlinks
to PDF files; Updated trademark information. Assigned a new Doc ID - DS726 to
replace old Doc ID - DS404. Another data sheet already had the DS404 number.
Notice of Disclaimer
.Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of
any kind, express or implied. Xilinx makes no representation that the Information, or any particular
implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you
may require for any implementation based on the Information. All specifications are subject to change without
notice. XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
ADEQUACY OF THE INFORMATION OR ANY IMPLEMENTATION BASED THEREON, INCLUDING BUT
NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
FROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR
FITNESS FOR A PARTICULAR PURPOSE. Except as stated herein, none of the Information may be copied,
reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means
including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior
written consent of Xilinx.
12
www.xilinx.com
DS726 April 24, 2009
Product Specification