DS726 Datasheet, PDF (2/12 Pages) Xilinx, Inc – OPB to PLBV46 Bridge

OPB to PLBV46 Bridge (v1.01a)
Features (contd)
• OPB Slave interface
- 32-bit OPB Slave interface that responds to byte enable transfers only. (Does not support dynamic
bus sizing or non-byte enable transactions.)
- Decodes up to four separate address ranges
- PLBV46 and OPB clock periods may have a 1:1 or 1:2 synchronous relationship.
- Utilizes read prefetch and OPB retries to eliminate deadlock and increase PLB bus performance.
• Utilizes post write buffer to improve performance.
Functional Description
Overview
Figure 1 provides a high-level overview of the OPB to PLBV46 Bridge.
OPB transactions are received and decoded in the OPB slave and data sent or received to or from the
appropriate buffer. The bridge controls the operation of the slave and implements the read prefetching
and posted writes. As a result the bridge effectively de-couples the OPB and PLB buses to improve the
PLB performance and eliminate the typical read lockup potential.
Figure Top x-ref 1
PLBv46 Clock Domain
PLBv46
PLB Clock Domain
plbv46_master_burst_v1_00_a
32-bit Native Data Width
16 x 32 FIFO
16 x 32 FIFO
Bridge
OPB Clock Domain
OPB
opb_slave
Figure 1: OPB PLBV46 Bridge in 1:2 Clock Ratio Configuration
DS404_01_091708
Clocking
The bridge provides for a PLBV46:OPB clock period ratio of 1:1 or 1:2. The bridge implementation
requires that the clocks be generated by one DCM. This insures that the rising edges of the PLBv46 and
OPB clocks are aligned and that the necessary and proper period constraint is applied to signals that
cross time domain boundaries.
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DS726 April 24, 2009
Product Specification