DS726 Datasheet, PDF (7/12 Pages) Xilinx, Inc – OPB to PLBV46 Bridge

OPB to PLBV46 Bridge (v1.01a)
Read Transactions
On receipt of the OPB master read transaction indication, the OPB slave captures the address and OPB
seqAddr qualifier, then asserts Sl_retry to force the master off the bus. It then blocks any further
requests using Sl_retry. Simultaneously it makes a fixed size read request to the
plbv46_master_burst of 1 or 16 words ¹. The OPB only has an indeterminate burst operation, therefore
the bridge must over read to fulfill the future transaction retry that will claim the data.
When the original master ² (that initiated the prefetch) returns to bus, it will gain access to the slave by
presenting a matching address to the original prefetch request. The slave delivers data to the master
until it deasserts the OPB_select signal (ending the transaction normally) or the prefetch buffer
empties. The buffer might empty early (and contain < 16 words) if a 16-word prefetch would have
accessed data beyond the end of the address range. The result is that all data up to the end of the
address range would be transfer-acknowledged to the OPB Master, but nothing beyond that.
If the plbv46_master_burst signals an error at the completion of the read prefetch attempt, the slave will
capture this status and clear the prefetch buffer. When the original master returns to claim the prefetch
data, it will receive an OPB_errAck assertion. Per OPB protocol, the OPB_errAck asserts concurrently
with the OPB_xferAck. Upon the selection of the slave, the master will see a continuous stream of
OPB_xferAcks until deselection.
Multiple read prefetches may be required for long read bursts. OPB masters must be careful when
performing read bursts at address locations which have read side effects because of the prefetching
feature (coherency or destructive read problems). Single beat reads should be used when accessing any
special memory locations, such as peripherals that destroy the contents of a register when it is read.
The prefetch timeout counter (of width determined by C_PREFETCH_TIMEOUT) starts counting
down as soon as the plbv46_master_burst has returned valid data (or an error) to the bridge. The OPB
master has until the timer expires to retrieve all of the data. If the timer expires in the middle of a
transaction, it will clear the prefetch buffer without returning an error.
PLBV46 Interface
The plbv46_master_burst_v1_00_a pcore services bridge requests for access to the PLB.
The bridge does not utilize the plbv46_master_burst bus lock feature.
Reset
The user must ensure that both sides of the bridge are reset simultaneously with overlapping reset
signals. The bridge is not designed to recover from independently applied resets.
1. When OPB_seqAddr=0 the bridge knows the explicit size of the read request is 1. In all other cases, the read
length is unknown and the bridge resorts to reading in16, 32-bit word chunks.
2. It is important to recognize that the original master may not be the one that gets the repeated transaction. If two
masters want to read from the same address, then the first may kick off the read prefetch, but the second may
actually receive the data upon retry. The bridge has no way to qualify the address with the master that initiated
the request. This condition is extremely unlikely. However, no harm should result because further read attempts
by the first master would simply result in a brand new prefetch.
DS726 April 24, 2009
www.xilinx.com
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Product Specification