DS726 Datasheet, PDF (5/12 Pages) Xilinx, Inc – OPB to PLBV46 Bridge

OPB to PLBV46 Bridge (v1.01a)
Table 1: PLBv46 Master Burst IO Signal Description (Contd)
Signal Name
Interface
Signal
Type
Init
Status
Description
Sl_xferAck
OPB
O
Slave transfer
acknowledge
Sl_beAck
OPB
O
Byte enable transfer
acknowledge
Sl_errAck
OPB
O
Error Acknowledge
Sl_retry
OPB
O
Asserted high to force
master off the bus.
Sl_DBus(0:31)
OPB
O
Read data sent back to bus
Sl_toutSup
OPB
O
Time out suppress
OPB System signals
OPB_Clk
OPB
I
OPB Clock domain
OPB_Rst
OPB
I
OPB slave reset.
Notes:
1. This function and timing of this signal is defined in the IBM 128-Bit Processor Local Bus Architecture
Specification Version 4.6.
2. Output ports that are not used are driven to constant logic levels that are consistent with the inactive state
for the subject signal. Input ports that are required but not used are internally ignored by the design.
3. For Fixed Length Burst requests, the starting address for the request as specified by the
IP2Bus_Mst_Addr(0:31) input must be aligned on an address boundary matching the
C_MPLB_NATIVE_DWIDTH value.
OPB Slave Interface
Single Transaction Bridging
The OPB slave must complete a transaction before it will accept a new read or write transaction. It
responds with the assertion of Sl_retry to each master request until the previous transaction is
successfully bridged. A new read is a transaction to an address that is different than the one currently
being prefetched. Every write is considered to be a new write irrespective of address. Successfully bridged
means the plbv46_master_burst had an opportunity at delivering the transaction to the PLB slave and
returned a status of success or failure. Sl_toutSup is not used to suppress the OPB bus timeout while
the bridge attempts to perform a read transaction.
For write transactions, a successfully bridged transaction is complete when the posted write buffer has
been emptied by the plbv46_master_burst.
For read transactions, a successfully bridged transaction is complete after the read prefetch is satisfied
(either with data or an error indication), a new request with an address satisfying the original prefetch
address matches, and the prefetch data is used partially or fully to satisfy the request.
If the prefetch buffer address does not receive a match in a specified time period, a prefetch match
timeout error occurs, which results in a flush of the prefetch buffer (and any error status) and a return
to accepting transactions. ¹
1. The user must set the C_PREFETCH_TIMEOUT parameter to a value that balances between stalling access to
the bridge and thrashing the read prefetch buffer.
DS726 April 24, 2009
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