DS726 Datasheet, PDF (4/12 Pages) Xilinx, Inc – OPB to PLBV46 Bridge

OPB to PLBV46 Bridge (v1.01a)
Table 1: PLBv46 Master Burst IO Signal Description (Contd)
Signal Name
Interface
Signal
Type
Init
Status
Description
PLB_MSSize(0:1)
PLB Bus I
Unused
See table note 2
PLB_MaddrAck
PLB Bus I
PLB_Mrearbitrate
PLB Bus I
PLB_MTimeout
PLB Bus I
PLB_MRdErr
PLB Bus I
PLB_MWrErr
PLB Bus I
PLB_MRdDBus(0:C_MPLB_DWIDTH
-1)
PLB Bus
I
See table note 1.
PLB_MRdDAck
PLB Bus I
PLB_MWrDAck
PLB Bus I
PLB_RdBTerm
PLB Bus I
PLB_MWrBTerm
PLB Bus I
PLB Signal Ports Included in the Design, but Unused Internally
M_TAttribute(0 to 15)
PLB Bus O
’0’
M_lockerr
PLB Bus O
’0’
M_abort
PLB Bus O
’0’
M_UABus(0:31))
PLB Bus O
zeros
Unused. See table note 2.
PLB_MBusy
PLB Bus I
PLB_MIRQ
PLB Bus I
PLB_RdWdAddr(0:3)
PLB Bus I
OPB Signals
OPB_select
OPB
I
Slave select
OPB_RNW
OPB
I
Read=1, Write=0
OPB_BE(0:3)
OPB
I
Byte Enables
OPB_beXfer
OPB
I
Unused
OPB_hwXfer
OPB
I
Unused
OPB_fwXfer
OPB
I
Unused
OPB_dwXfer
OPB
I
Unused
OPB_seqAddr
OPB
I
Sequential Address (burst)
indication
OPB_ABus(0:31)
OPB
I
Transaction address
OPB_DBus(0:31)
OPB
I
Write data arriving from the
bus.
4
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DS726 April 24, 2009
Product Specification