DS726 Datasheet, PDF (3/12 Pages) Xilinx, Inc – OPB to PLBV46 Bridge

OPB to PLBV46 Bridge (v1.01a)
Deadlock Prevention
Deadlock can occur when masters request their bridges to attempt read transactions at the same time
and the OPB slave on the OPB to PLB bridge utilizes timeout suppression. It starts when the PLB to
OPB bridge addrAcks a read transaction before it knows the OPB will be busy, thus tying up the PLB
read bus. (There is no timeout on the PLBV46 once the address phase completes.) Simultaneously, an
OPB master connects to the OPB to PLB bridge slave for a read and uses timeout suppression to block
further access to the OPB until its read completes. However, its read will never complete because the
PLB read bus is locked by the other bridge. The read attempts result in total locking of both buses.
The solution used by the OPB to PLB bridge involves decoupling the buses through the use of a posted
write buffer and a read prefetch buffer. With this solution the system does not require the use of OPB
timeout suppression and no inter-bridge communication is needed to eliminate the potential for
deadlock.
PLBv46 Master Burst IO Signals
Table 1: PLBv46 Master Burst IO Signal Description
Signal Name
Interface
Signal
Type
PLB Clock and Reset
Init
Status
MPLB_Clk
PLB Bus
I
MPLB_Rst
PLB Bus
I
Other System Signal
MD_error
PLB Bus
O
’0’
PLB Request and Qualifier Signals
M_request
PLB Bus
O
’0’
M_priority
PLB Bus
O
’0’
M_buslock
PLB Bus
O
’0’
M_RNW
PLB Bus
O
’0’
M_BE(0:[C_MPLB_DWIDTH/8]-1)
PLB Bus
O
zeros
M_Msize(0:1)
PLB Bus
O
"00"
M_size(0:3)
PLB Bus
O
"0000"
M_type(0:2)
PLB Bus
O
"000"
M_ABus(0:31)
PLB Bus
O
zeros
M_wrBurst
PLB Bus
O
’0’
M_rdBurst
PLB Bus
O
’0’
M_wrDBus(0:C_MPLB_DWIDTH-1)
PLB Bus
O
zeros
PLB Reply Signals
Description
PLB main bus clock.
See table note 1.
PLB main bus reset.
See table note 1.
Master Detected Error
Status Output
See Table note 2.
DS726 April 24, 2009
www.xilinx.com
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Product Specification