DS726 Datasheet, PDF (8/12 Pages) Xilinx, Inc – OPB to PLBV46 Bridge

OPB to PLBV46 Bridge (v1.01a)
Design Parameters
Table 2: Bridge Design Parameters
Feature/Description
Parameter Name
Allowable
Values
Decoder Address Range Definition
Number of Address Ranges
C_ NUM_ADDR_RNG
1-4
Address range definition base
address
C_RNGn_BASEADDR
(0 <= n <= 3)
0x00000000
to
0xFFFFFFFF
Address range definition high address
C_RNGn_HIGHADDR
(0<=n<=3)
0x00000000
to
0xFFFFFFFF
Bridge Configuration
Establishes the ratio of PLB to OPB
bus clock periods. The clocks must be
synchronous with minimal phase
difference.
C_BUS_CLOCK_
PERIOD_RATIO
1=1:1, 2=1:2
Specifies the width of the timeout
counter that determines the amount
of time (in PLBV46 clocks) the bridge
waits for a master to retrieve all the
read prefetch data before the prefetch
buffer is flushed and new transactions
are accepted again.
C_PREFETCH
_TIMEOUT
5-32
PLB I/O Specification
Specifies the Number of Used
Address bits out of the available 64 C_MPLB_AWIDTH
32
bits of PLBV46 addressing
Width of the PLB Data Bus to which
the Master is attached
C_MPLB_DWIDTH
32, 64, 128
Specifies the internal native data
width of the Master
C_MPLB_NATIVE
_DWIDTH
32
FPGA Family Type
Xilinx FPGA Family
C_FAMILY
spartan3,
virtex4, virtex5
Default
Values
VHDL
Type
1
integer
X"FFFFFFFF"
std_logic_
vector
X"00000000"
std_logic_
vector
1
integer
10
integer
32
integer
32
integer
32
integer
"virtex4"
string
Allowable Parameter Combinations
The current implementation of the PLBV46 Master Burst has the following restrictions which apply to
parameter value settings:
• The assigned value for C_MPLB_AWIDTH is currently restricted to 32.
• The assigned value for C_MPLB_NATIVE_DWIDTH is currently restricted to 32.
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DS726 April 24, 2009
Product Specification