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DS726 Datasheet, PDF (6/12 Pages) Xilinx, Inc – OPB to PLBV46 Bridge
OPB to PLBV46 Bridge (v1.01a)
The bridge does not support byte or halfword bursting on the OPB bus. Bursts must start on a word
aligned address (address bits 30 to 31 = ’00), end on a word aligned address, must and contain only full
word data.
The bridge drives valid byte enables onto the PLBV46 only when it detects a single write or single read.
It does this by examining OPB_seqAddr. When OPB_SeqAddr=0, it assumes a single transaction with
byte enables. Xilinx OPB masters that use the Xilinx IPIF are known to follow this assumption.
Otherwise a PLBv46 burst is used and the OPB_be() signal is ignored.
Address Decode Cycle
OPB transactions begin with an address decode cycle. A design parameter allows the user to specify the
number of address ranges the bridge will respond to. Each range has two parameters,
C_RNGn_BASEADDR and C_RNGn_HIGHADDR, that specify the 32-bit lower and upper boundary
for that range. These parameters define that portion of the total system address space to which the OPB
slave will respond.
Write Transactions
When an OPB Master requests write access to the bridge, the slave immediately accepts from 1 to 16 full
words of data, then buffers the data. The bridge will not accept write data that is addressed beyond the
end of an address range, even if the ranges are back-to-back. For a single word write, indicated by the
deassertion by the master of OPB_seqAddr, the slave captures the byte enable pattern,
OPB_ABus(0:29), and Sl_xferAcks the word. If OPB_seqAddr=1, then the slave counts the
number of words written to the buffer to provide the plbv46_master_burst with the fixed length for a
write burst on the PLB bus. Byte enables are ignored for PLB burst operations, therefore the OPB master
should ensure that all byte enables are asserted high when OPB_seqAddr is asserted high.
After signaling a write request to the plbv46_master_burst (of either a single or burst), the OPB slave
blocks (by issuing retries) until it receives confirmation of the PLB operation complete status.
The nature of posted writes prohibits the return of an PLB transaction failure to the OPB master that
originated the request. Any error status is therefore lost.
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DS726 April 24, 2009
Product Specification