DS614 Datasheet, PDF (9/9 Pages) Xilinx, Inc – Clock Generator

Clock Generator (v4.03a)
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Revision History
Date
5/15/07
1/16/08
4/22/08
7/25/08
3/31/09
6/24/09
12/2/09
4/19/10
12/14/10
6/22/2011
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1/18/2012
1.10
Description of Revisions
Initial Xilinx release.
Released v2.00a; added PLL support.
Released v2.01a; added Automotive SP3E, SP3A, SP3, and SP3A DSP support.
Added QPro Virtex-4 Hi-Rel, QPro Virtex-4 Rad Tolerant, and SP-3AN support.
Release v3.00a, changed C_CLK_GEN parameter, removed obsolete parameters.
Released v3.01a; added MMCM support.
Released v3.02a for EDK_L 11.4.
Released v4.00a for EDK 12.1; removed low-level internal view parameters.
Released v4.01a for EDK 12.4.
Released v4.02a for EDK 13.2; added 7 Series support; incorporated CR592667.
Released v4.03a for EDK 13.4; changed data type of CLKOUTi_PHASE, CLKFOUTi_PHASE
to real from integer.
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DS614 January 18, 2012
www.xilinx.com
9
Product Specification