DS614 Datasheet, PDF (6/9 Pages) Xilinx, Inc – Clock Generator

Clock Generator (v4.03a)
Parameter - Port Dependencies
Table 3 shows the effect of setting various parameters.
Table 3: Clock Generator Parameter-Port Dependencies
Parameter
Port
Description
C_CLKIN_FREQ CLKIN and all output ports If C_CLKIN_FREQ is 0, clock_generator has no function.
C_CLKOUTi_FREQ CLKOUTi (i=0,..,15)
If C_CLKOUTi_FREQ is 0, CLKOUTI is not used and the corresponding
C_CLKOUTi_BUF, C_CLKOUTi_GROUP,
C_CLKOUTi_VARIABLE_PHASE, and C_CLKOUTi_PHASE are ignored.
C_CLKFBIN_FREQ CLKFBIN, CLKFBOUT
If CLKFBIN_FREQ is 0, all the ports and corresponding parameters of the
sync up function module are ignored. Refer to the clock sync up section for
details.
Clock Circuitry Generation Algorithm
On Spartan-3 and Virtex-4 FPGAs, DCM is used for clock generation and clock sync-up; on Virtex-5 and Spartan-6
FPGAs, PLL and DCM is used for clock generation and DCM for clock sync-up; on Virtex-6 FPGAs, MMCM is used
for clock generation and clock sync-up. On 7 Series FPGAs, MMCM and PLLE2 are used for clock generation and
MMCM is used for clock sync-up. The clock sync-up function always uses one dedicated resource, either DCM or
MMCM. The clock generation algorithm adopts the following guidelines:
• Use as few clock resource of DCM, PLL or MMCM as possible
• When multiple resources are used, the preference is to put them in parallel rather than cascading them
• If cascading, do one level at the most
Static Phase Shift
Phase shift is set directly to the clock resource, as is set on the Clock Generator core.
When there are two (2) CLKOUTi signals with the same frequency, but with opposite phase alignment, the
algorithm uses inverter logic to generate one clock from the other.
De-skew among Clock Outputs
When a multiple CLKOUTi signal needs to be phase aligned, set the corresponding C_CLKOUTi_GROUP
parameters to the same value. For example, given the following parameters:
Parameter C_CLKOUT0_GROUP = pll0
Parameter C_CLKOUT1_GROUP = pll0
The generation algorithm will ensure that CLKOUT0 and CLKOUT1 are from same PLL and that the instance name
of that PLL is "pll0".
When phase alignment is not required, set C_CLKOUTi_GROUP to "NONE".
For a design with the EDK PowerPC^® 440 core, when the C_CLKOUTi_GROUP parameter of a CLKOUTi port is set
to PLL0_ADJUST or PLL1_ADJUST, the algorithm sets the C_COMPENSATION parameter of the PLLs to
"SYSTEM_SYNCHRONOUS".
DS614 January 18, 2012
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