DS614 Datasheet, PDF (7/9 Pages) Xilinx, Inc – Clock Generator

Clock Generator (v4.03a)
Dynamic Phase Shift
Dynamic phase shift is supported only on Virtex-6 and 7 Series FPGAs. Below is an example how to use dynamic
phase shift.
PARAMETER C_CLKOUT3_VARIABLE_PHASE = TRUE
PARAMETER C_PSDONE_GROUP = MMCM1_FB
PARAMETER C_PSDONE_GROUP = MMCM1_FB
In this example, CLKOUT3 of the Clock Generator core is the dynamic phase shift port, PSDONE of one MMCM
that connects to PSDONE of the Clock Generator core. That MMCM is named "MMCM1" and its feedback is
dynamically phase shift. Another is shown below.
PARAMETER C_CLKOUT3_VARIABLE_PHASE = TRUE
PARAMETER C_PSDONE_GROUP = MMCM1
In the second example, CLKOUT3 of the Clock Generator core is the dynamic phase shift port, PSDONE, of one
MMCM that connects to PSDONE of the Clock Generator core. That MMCM is named "MMCM1" and its feedback
is not dynamically phase shift.
Restrictions
Because the proposed target function of the Clock Generator core is ease-of-use rather than functional
completeness, not all the clock functions provided by DCM, PLL, MMCM, and clocking buffer are available in the
Clock Generator core. For example, it does not utilize CLKIN2 of MMCM_ADV on the Virtex-6 device.
In addition, the Clock Generator core does not explore all possible scenarios of clock circuitry, so it is likely that a
system designer can devise circuitry manually. In that case, the Clock Generator core will not be able to identify any
working circuitry and will report a failure.
Differences Between Clock Generator v3.02a and v4.01a
Because low level parameters were removed from v4.00a of the Clock Generator, the user is not able to directly
manipulate the final clock circuitry in the MHS file and must rely on the core algorithm to generate the circuitry.
The Clock Generator v4.01a has all the high level parameters of v3.02a. To migrate the design with the Clock
Generator v3.02a to Clock Generator v4.01a, change the core version from 3.02a to 4.01a. Please note that the
delineated procedure does not work if the low level parameters of v3.02a are used (PARAMETER C_CLK_GEN is
defined in the design and its value is not "UPDATE").
Differences Between Clock Generator v4.00a and v4.01a
Because parameter C_CLK_PRIMITIVE_FEEDBACK_BUF has been added to v4.01a, setting this parameter to
TRUE causes BUFG to be inserted into the self feedback paths of all clock resources. This setting brings better phase
alignment between CLKIN and CLKOUTi. The default value is FALSE.
To migrate the design with the Clock Generator v4.00a to the Clock Generator v4.01a, change the core version from
4.00a to 4.01a only.
DS614 January 18, 2012
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