DS614 Datasheet, PDF (3/9 Pages) Xilinx, Inc – Clock Generator

Clock Generator (v4.03a)
Lock Output
When there is one clock resource only, its LOCK port is directly connected to the Clock Generator core LOCK port.
When there are multiple clock resources cascaded, their LOCK outputs are connected to AND logic and the output
of the AND logic connects to the LOCK port of the Clock Generator core. Figure 2 shows a combination of
cascading and parallel clock resources.
X-Ref Target - Figure 2
CLOCK GENERATOR
CLKIN
CLKIN LOCKED
RST
LOCKED
LOCKED
CLKIN LOCKED
Figure 2: Reset Connection Example
DS614_02
If clock requirements cannot be met, the LOCKED output signal remains inactive and the output clocks are
undetermined.
With the Spartan^®-6 FPGA, the Clock Generator core needs to have only two (2) PLL cascaded. The LOCK of the
second PLL directly connects to LOCK of the Clock Generator core.
Clock Sync-up
The Clock Generator core provides clock sync-up function for an input clock and for one of the required clocks. The
input clock is through clock port, CLKFBIN and its frequency is defined in parameter C_CLKFBIN_FREQ.
With non-Virtex^®-6 and non-7 Series FPGAs, the Clock Generator core uses the algorithms listed below to generate
the sync-up circuitry:
1. Generate a DCM dedicated for this sync-up function.
2. Connect CLKFBIN to CLKIN of the DCM.
3. Go through the required clocks in the sequence: CLKOUT0, CLKOUT1, CLKOUT2, and so forth.
4. Select the first one with same frequency as CLKFBIN as defined by C_CLKFBIN_FREQ.
5. Connect the selected clock to CLKFB of the DCM.
6. Connect CLK0 of the DCM to CLKFBOUT.
On Virtex-6 and 7 Series FPGAs, the Clock Generator core uses the algorithms listed below to generate the sync-up
circuitry:
1. Generate a MMCM dedicated for this sync-up function.
2. Connect CLKFBIN to CLKIN of the MMCM.
3. If parameter C_CLKFBIN_DESKEW is set to one of 16 CLKOUTi, select that parameter and proceed to step 6;
if not, proceed to step 4
4. Go through the required clocks in the sequence: CLKOUT0, CLKOUT1, CLKOUT2, and so forth.
5. Select the first one with same frequency as CLKFBIN as defined by C_CLKFBIN_FREQ.
6. Connect the selected clock to CLKFB of the MMCM.
7. Connect CLKFBOUT of the MMCM to CLKFBOUT.
DS614 January 18, 2012
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