DS614 Datasheet, PDF (8/9 Pages) Xilinx, Inc – Clock Generator

Clock Generator (v4.03a)
Differences Between Clock Generator v4.01a and v4.02a
The Clock Generator v4.02a has all the high level parameters of the v4.01a. To migrate the design with Clock
Generator v4.01a to Clock Generator v4.02a, change the core version from 4.01a to 4.02a.
New parameters, C_CLKOUT0_DUTY_CYCLE to C_CLKOUT15_DUTY_CYCLE, have been added to v4.02a. The
default value of these parameters is “0.5”. The user is not allowed to change these parameters from SAV by clicking
on clock_generator v4.02a. The PLLE0 group has been added to the list of all C_CLKOUT*_GROUP.
Migrating Clock Generator from v4.02a to v4.03a
The Clock Generator v4.03a has all the high level parameters of the v4.02a. To migrate the design with Clock
Generator v4.02a to Clock Generator v4.03a, change the core version from 4.02a to 4.03a.
No new parameter have been added to v4.03. The data type of C_CLKOUTi_PHASE and C_CLKFBOUT_PHASE
have been changed from integer to real.
Design Implementation
Target Technology
The target technology is an FPGA listed in the Supported Device Family field of the LogiCORE IP Facts Table.
Device Utilization and Performance Benchmarks
The device utilization depends on the number of output clocks used and the value of the parameters of each output
clock. Up to 4 DCM modules, 2 PLL modules and 4 MMCM modules may be instanced with BUFGs, clock
inverters, and reset logics. See respective FPGA family user guide for details on DCM, PLL, MMCM, and BUFG
primitive performance and available resources.
In one Clock Generator v4.03a module:
• All 7 Series FPGAs will use up to 4 MMCMs and 1 PLLE2
• Virtex-6 family FPGAs will use up to 4 MMCMs (no DCM or PLL)
• Virtex-5 and Spartan-6 family FPGAs will use up to 2 PLLs and 4 DCMs (no MMCM)
• All other FPGA families will use up to 4 DCMs (no PLL or MMCM)
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE Design Suite Embedded
Edition software under the terms of the Xilinx End User License. The core is generated using the Xilinx ISE
Embedded Edition software (EDK). For more information, please visit the Clock Generator product web page.
DS614 January 18, 2012
www.xilinx.com
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Product Specification