DS614 Datasheet, PDF (5/9 Pages) Xilinx, Inc – Clock Generator

Clock Generator (v4.03a)
Table 1: Clock Generator Parameters (Cont’d)
Parameter Name
Feature Description
Allowable Values
C_CLK_GEN
C_FAMILY
C_DEVICE
C_PACKAGE
C_SPEEDGRADE
Set the value to UPDATE to generate for
generation algorithm to generate
circuitry. The generation algorithm sets
the value to PASSED or FAILED in the
generated VHDL source indicating the
result.
UPDATE, PASSED, FAILED
The EDK tool sets the parameter. User
assignment is ignored.
Check the Clock generator
MPDs
ARCH_SUPPORT_MAP for
complete FPGA family
support.
Specify the target FPGA device.
Valid FPGA device.
Specify the target FPGA package.
Valid FPGA package.
Specify the target FPGA speed grade. Valid FPGA speed grade
Notes:
1. See detailed descriptions in the subsequent sections.
2. See detailed descriptions and examples in the subsequent sections and in Table 2.
Default
VHDL
Type
UPDATE string
virtex6 string
NOT_SET
NOT_SET
NOT_SET
string
string
string
I/O Signals
The interface signals for the Clock Generator core module are listed and described in Table 2.
Table 2: Clock Generator Signal Descriptions
Signal Name I/O
Initial
State
Description
CLKIN
I
Connect to CLKIN of DCM, PLL, or MMCM.
CLKOUTi: i=0 -15 O
Low
Connect to the clock output port of a DCM, PLL, or MMCM optionally through a
BUFG or an inverter.
CLKFBIN
I
Connect to CLKFB of DCM or the CLKFBIN port of an MMCM.
CLKFBOUT
O
Low Connect to the CLK0 port of a DCM or the CLKBOUT port of an MMCM.
LOCKED
O
Low LOCKED = High indicates that all required clocks are stable.
PSCLK
I
Connect to PSCLK of MMCM. Applicable for Virtex-6 and 7 Seriees devices only.
PSEN
I
Connect to PSEN of MMCM. Applicable for Virtex-6 and 7 Series devices only.
PSINCDEC
I
Connect to PSINDEC of MMCM. Applicable for Virtex-6 and 7 Series devices only.
PSDONE
O
Connect to PSDONE of MMCM. Applicable for Virtex-6 and 7 Series devices only.
RST
I
If C_EXT_RESET_HIGH = 0, an inverter is inserted; otherwise, this signal is
connected to the reset port of the DCM, PLL, PLLE or MMCM.
DS614 January 18, 2012
www.xilinx.com
5
Product Specification