DS614 Datasheet, PDF (2/9 Pages) Xilinx, Inc – Clock Generator

Clock Generator (v4.03a)
Conventions for this Document
Because the Clock Generator core has 16 output clocks named CLKOUTi in which "i" is 0 to 15, CLKOUTi is used to
refer to any of the 16 clock output ports named in this document.
Functional Description
The Clock Generator core design framework is shown in Figure 1 and described in the following sections.
X-Ref Target - Figure 1
CLKIN
Generate Requested
Clock Input
Clock Resource
CLKOUTi
Clock Resource
CLKOUTi
CLKFBIN
RST
Sync up
CLKFBOUT
LOCK
DS614_01
Figure 1: Clock Generator Modules Block Diagram
Clock Input
The Clock Generator core has one input clock port, CLKIN. It is the clock source for the overall clocking circuitry in
the Clock Generator core. The driving clock for the clock input can be from the off-chip or in-chip source. The
system designer decides whether a clocking buffer should be used for the driving clock. The Clock Generator core
does not insert a buffer for the CLKIN.
Clock Circuitry to Generate the Requested Clock Outputs
Clock circuitry is dynamically generated based on clock requirement and target FPGA architecture. There could be
up to 4 DCM, 2 PLL or 4 MMCM used in the circuitry, depending on the architecture.
The generation algorithm is called by EDK PlatGen and Simgen when the EDK user translates the EDK design to
netlist design. The generated VHDL source file is at <project
directory>/hdl/elaborate/<clock_generator instance name>_<clock_generator
version>/hdl/vhdl.
Reset Input
The Clock Generator core connects the reset input port, RST, to the reset input ports of the clock resource in the
generated circuitry, for example, the reset port of DCM, reset port of PLL and reset port of MMCM. When there are
cascaded clock resources, the reset port of the clock resource at the downstream is driven by the lock output from
upstream clock resource.
DS614 January 18, 2012
www.xilinx.com
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Product Specification