DS604 Datasheet, PDF (9/12 Pages) –

3GPP2 Turbo Encoder v2.0
When a valid-FD is sampled, the RFFD signal is driven Low to indicate that the core is no longer wait-
ing for FD_IN. The block size, in this case n, of the current input block is sampled on the BLOCK_SIZE
port, and the first data symbol, d1, is sampled on the DATA_IN port.
A High on the ND port indicates that the value on the DATA_IN port is new data. If ND is sampled Low,
then the DATA_IN port is not sampled, and the internal write address does not advance.
The core continues to input data, until n new data samples have been accepted, whereupon RFD is nor-
mally driven Low to indicate that the core is no longer ready for data and the core stops sampling the
DATA_IN port.
DWhen the core is ready to accept a new block of data, RFFD and RFD are both driven High. The time at
which this occurs is determined by how long it takes the core to output the current output block, which
depends on its block size, and on whether or not the output side of the core is inhibited by negating
i^{RFD_IN. If the input operation completes and the output cycle is already complete, it is possible for}
s^{RFFD to be asserted, and a new input cycle to be started without RFD going Low.}
After asserting RFFD, the core waits until the next valid-FD is sampled, whereupon a write cycle is
cstarted, in this case, with block size N.
The behavior of the core is not specified if, on a valid-FD, an invalid BLOCK_SIZE_SEL is sampled, or
o _{RFFD is sampled Low (core not ready for a new block). However, the core will recover if a valid-FD is}
sampled, with a valid BLOCK_SIZE_SEL value when RFFD is High.
n _{Trellis Termination}
During the first three tail bit periods, RSC2 is disabled and the control switch of RSC1 is set to the lower
t _{position to output the RSC1 tail bits on the RSC1 systematic and parity outputs. During the last three}
i _{tail bit periods, RSC1 is disabled and the control switch of RSC2 is set to the lower position to output}
n _{the RSC2 tail bits on the RSC2 systematic and parity outputs.}
The RSC2 systematic tail bits are also output on the RSC1 Systematic output. Typically, the RSC2 sys-
u tematic data is only transmitted during the tail bit period, so by multiplexing the RSC2 systematic data
onto the RSC1_SYSTEMATIC port, the user can usually ignore the RSC2_SYSTEMATIC port. However,
it is provided to maximize flexibility.
e _{Output Control Signals}
d _{The RDY signal is driven High to indicate that there is valid data on the systematic and parity ports. In}
addition, the RSC1_TAIL and RSC2_TAIL outputs are provided to indicate trellis termination of RSC1
and RSC2, respectively. A High on RSC1_TAIL indicates that RSC1 tail bits are being output, and a
High on RSC2_TAIL indicates that RSC2 tail bits are being output. The output timing is shown in
IP _{Figure 6.}
Flow control on the output side can be implemented with the optional RFD_IN input port. If the
RFD_IN port is sampled Low on an active rising clock edge, the RSC output ports, RDY, and the internal
circuitry associated with these outputs are frozen.
The input side of the core is not directly affected by the RFD_IN port. However, if RFD_IN is deasserted
often enough, the time taken to output a block can be extended such that the assertion of RFFD is
delayed, which acts to prevent overrun on the input side.
RSC1_PARITY1 and RSC2_PARITY1 have the same timing as RSC1_PARITY0 and RSC2_PARITY0,
respectively.
DS604 April 2, 2007
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9
Product Specification