DS604 Datasheet, PDF (1/12 Pages) –

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3GPP2 Turbo Encoder v2.0
DS604 April 2, 2007
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Product Specification
Features
LogiCORE Facts
• Drop-in module for Virtex™-II, Virtex-II Pro,
Virtex-4, Virtex-5, Spartan™-3, Spartan-3E,
Spartan-3A/3AN/3A DSP FPGAs
D• Implements the 3GPP2/CDMA-2000 Turbo Encoder
specification [1]
• Double-buffered symbol memory for maximum
i^throughput
s • Flexible interfacing by means of optional control
signals
c _Applications
o ^{The 3GPP2 Turbo Encoder core can be used in conjunc-}
tion with the Xilinx 3GPP2 Turbo Decoder (available
from the Xilinx CORE Generator™ system) to provide
n _{an extremely effective way of transmitting data reliably}
under low signal-to-noise conditions and to provide a
t ^{performance close to the theoretical optimal perfor-}
i ^{mance as defined by the Shannon limit.}
n _{General Description}
The 3GPP2 Turbo Encoder core is a parallel implemen-
u _{tation of the convolutional turbo encoder specified by}
the 3GPP2/CDMA-2000 Turbo Encoder specification
e [1].
The theory of operation of the Turbo Codes is described
d in the paper by Berrou, Glavieux, and Thitimajshima
IP ^[2].
Core Specifics
Supported Device
Family
Virtex-II, Virtex-II Pro, Virtex-4,
Virtex-5, Spartan-3, Spartan-3E,
Spartan-3A/3AN/3A DSP
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Verification
VHDL Structural (UniSim) Model
Verilog Structural (UniSim) Model
Instantiation Template
VHDL Wrapper
Verilog Wrapper
Design Tool Requirements
Xilinx Implementation
Tools
ISE™ 9.1i or higher
Licensing
Pay Core. Requires a full or evaluation license
Support
Provided by Xilinx, Inc @ www.xilinx.com
© 2004-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their
respective owners. Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard,
Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx
expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free
from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS604 April 2, 2007
www.xilinx.com
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Product Specification