DS604 Datasheet, PDF (2/12 Pages) –

3GPP2 Turbo Encoder v2.0
The 3GPP2 Turbo Encoder input and output ports are shown in Figure 1.
Figure Top x-ref 1
Mandatory Pins
CLK
RS C1_S YSTE MA TIC
FD_I N
RSC1_PARITY0
DATA _IN
B LOCK_ SIZE_SEL
Optional Pins
ND
D RFD_IN
A CL R
S CL R
CE
RS C1 _P ARITY1
RSC2_ SYS TEM ATIC
RSC2 _PA RI TY0
RS C2 _P ARITY1
RSC1 _TAI L
RSC2_TAIL
RDY
RFD
RFFD
is Multi-bit Signal
Single-bit Signal
DS604_01_020207
c Figure 1: TCC Encoder Pinout
o ^{The encoder architecture is shown in Figure 2. It is a block-based processing unit. Each block of data is}
processed in two identical Recursive Systematic Convolutional (RSC) encoders, which generate
high-weight codes. RSC1 processes the raw input data, while RSC2 processes an interleaved version of
n _{the input data. The coding operates on the principle that if an input symbol is corrupted in the}
sequence from RSC1, then it is unlikely also to be corrupted in the reordered sequence from RSC2, and
t ^{vice versa.}
i ^{The delay shown in Figure 2 is used to indicate that the input data is delayed before passing through}
n ^{RSC1. This ensures that the systematic data from RSC1 and RSC2 are block-aligned at the output. The}
input data is also double-buffered to maximize throughput.
u ^{Often some of the encoded output bits need not be transmitted, so they are omitted, or punctured from}
the output stream. Puncturing offers a dynamic trade off between code rate and error performance.
When the channel is noisy or the data requires more protection, extra redundancy can be added, low-
e _{ering the code rate. Puncturing is not implemented as part of the core.}
d _IP ^{FigureTopx-ref2}
D_I N
Delay
RSC1_systematic
RS C1 _p ar ity0
RSC1
RSC1_parity1
X_k
Z_k
W_k
Puncturing
(external to
Punctured
core)
Output
RS C2 _syst ematic
X’ _k
Interleaver
RSC2 RSC2_parity0
RSC2 _pa rit y1
Z’ _k
W’ _k
DS604_02_020207
Figure 2: TCC Encoder Structure
2
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DS604 April 2, 2007
Product Specification