DS604 Datasheet, PDF (5/12 Pages) –

3GPP2 Turbo Encoder v2.0
Table 2: I/O Ports (Continued)
Pin
Sense
Port
Width
(bits)
Description
RSC2_PARITY1
Output
1
RSC2_parity1 - The parity1 output from RSC2.
RSC1_TAIL
RSC2_TAIL
D_RDY
is_{RFD_IN}
Output
Output
Output
Input
(optional)
1
RSC1_tail - This indicates that the tail bits are being output on
RSC1 when asserted (High).
1
RSC2_tail - This indicates that the tail bits are being output on
RSC2 when asserted (High).
1
Ready - This indicates that there is valid data on the
systematic and parity outputs when asserted (High).
Ready For Data Input - An output strobe signal. When
deasserted (Low), the output side of the encoder is
1
suspended. The Systematic and Parity data outputs and the
associated control signals RDY, RSC1_TAIL and RSC2_TAIL
are frozen.
c_{Asynchronous Clear (ACLR)}
o _{The ACLR input port is optional. When ACLR is driven High, the core is reset to its initial state, i.e., the}
core is ready to process a new block. Following the initial configuration of the FPGA, the core is auto-
n ^{matically in the reset state, so no further ACLR is required before an encoding operation can take place.}
ACLR is the only asynchronous input to the core.
t Clock (CLK)
i With the exception of asynchronous clear, all operations of the core are synchronized to the rising edge
n of CLK. If the optional CE pin is enabled, an active rising clock edge occurs only when CE is High. If CE
is Low, the core is held in its current state.
u Clock Enable (CE)
Clock enable is an optional input pin that is used to enable the synchronous operation of the core.
e ^{When CE is High, a rising edge of CLK is acted upon by the core, but if CE is Low, the core remains in}
its current state. An active rising clock edge is on one which CE (if enabled) is sampled High.
d Synchronous Clear (SCLR)
The SCLR signal is optional. When it is asserted High on a valid clock edge, the core is reset to its initial
state, and the core is ready to process a new block. Following the initial configuration of the FPGA, the
core is automatically in the reset state, so no further SCLR is required before an encoding operation can
IP _{take place. If the CE input port is selected, SCLR is ignored when CE is Low.}
Data In (DATA_IN)
The DATA_IN port is a mandatory input port which carries the unencoded data. The input process is
started with a valid-FD signal and data is read serially into the DATA_IN port on a clock-by-clock basis.
Block size clock cycles are, therefore, required to input each block. DATA_IN may be qualified by the
optional ND port. (see below)
DS604 April 2, 2007
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5
Product Specification