DS604 Datasheet, PDF (4/12 Pages) –

3GPP2 Turbo Encoder v2.0
Table 1: Block Size Select Codes (Continued)
BLOCK_SIZE_SEL
Turbo Encoder Block Size
8
1000
4090
9
1001
5114
10
1010
11
1011
12
1100
6138
8186
12282
D_{Input/Output Ports}
i^{The I/O ports of the core are summarized in Table 2.}
s_{Table 2: I/O Ports}
Port
c_Pin
Sense Width
(bits)
Description
o _ACLR
Input
(optional)
1
Asynchronous Clear - When this is asserted (High), the
encoder is asynchronously reset.
n _CLK
Input
1
Clock - All synchronous operations occur on the rising edge of
the clock signal.
ti _CE
Input
(optional)
Clock Enable - When this is deasserted (Low), rising clock
1
edges are ignored and the core is held in its current state. A
valid clock edge’ is one on which CE is High.
n _SCLR
Input
(optional)
1
Synchronous Clear - When this is asserted (High) on a valid
clock edge, the encoder is reset.
u ^DATA_IN
Input
1
Data Input - This is the data to be encoded.
ND
Input
(optional)
1
New Data - When this is asserted (High) on a valid clock edge,
a new input value is read from the DATA_IN port.
e _{FD_IN}
Input
1
First Data - When this is asserted (High) on a valid clock edge,
the encoding process is started. Qualified by ND
d _{BLOCK_SIZE_SEL}
Input
Block Size Select - This 4-bit port, which is read when FD_IN
4
is sampled High, selects the block size to be encoded. See
Table 1.
IP _RFFD
Output
1
Ready For First Data - When this is asserted (High), the core
is ready to start another encoder operation.
RFD
Output
1
Ready For Data - When this is asserted (High), the core is
ready to accept input on the DATA_IN port.
RSC1_SYSTEMATIC Output
1
RSC1_systematic - The systematic output from RSC1.
RSC1_PARITY0
Output
1
RSC1_parity0 - The parity0 output from RSC1.
RSC1_PARITY1
Output
1
RSC1_parity1 - The parity1 output from RSC1.
RSC2_SYSTEMATIC Output
1
RSC2_systematic - The systematic output from RSC2.
RSC2_PARITY0
Output
1
RSC2_parity0 - The parity0 output from RSC2.
4
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DS604 April 2, 2007
Product Specification