DS604 Datasheet, PDF (8/12 Pages) –

3GPP2 Turbo Encoder v2.0
Figure Top x-ref 4
a) Effect of changing block size
FD_IN
RFFD
D _RFD
RDY
LOAD MEM1
OUTPUT MEM0
is_{b) Effect of ND and RFD_IN}
FD_IN
LOAD MEM0
OUTPUT MEM1
LOAD MEM1
OUTPUT MEM0
co_ND
RFD_IN
nti _RFFD
n _RFD
RDY
LOAD MEM1
OUTPUT MEM0
Extended by negating RF D_IN
Extended by negating ND
LOAD MEM0
OUTPUT MEM1
LOAD MEM1
OUTPUT MEM0
u _{Figure 4: Double-Buffered Mode Data Throughput}
e ^{Input Control Signals}
Figure 5 shows the signals associated with the data input side of the core. If, on an active rising edge of
d ^{CLK, FD_IN and ND (if selected) are both sampled High, this is known as a valid-FD, or valid First Data}
signal.
Figure Top x-ref 5
CLK
IP _FD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
BLOCK_SIZE
n
N
DATA_IN
X
d1 d2 X
d3 X
d4 ...
dn-2 dn-1 dn X
...
X
X
D1
ND
CE
RFFD
RFD
Figure 5: Input Timing
8
www.xilinx.com
DS604 April 2, 2007
Product Specification