DS604 Datasheet, PDF (6/12 Pages) –

3GPP2 Turbo Encoder v2.0
New Data (ND)
The optional ND signal is used to indicate that there is new input data to be read from the DATA_IN
port. For example, if the input block size is 122, then 122 active High ND-samples are required to load a
block of data into the encoder. ND is also used to qualify the FD_IN input. (see First Data (FD_IN)).
First Data (FD_IN)
FD_IN is a mandatory input port which is used to start the encoder operation. FD_IN is qualified by the
optional ND input. If ND is not selected, a valid-FD means simply that FD_IN is sampled High on an
active rising clock edge. If ND is selected, a valid-FD means that FD_IN and ND are both sampled High
Don an active rising clock edge.
When a valid-FD occurs, the first data is read from the DATA_IN port, and the value of the
BLOCK_SIZE_SEL port is sampled. The core then continues loading data until a complete block has
ibeen input.
s_{The FD_IN input should only be asserted when the RFFD output is High. (see Ready For First Data}
(RFFD)). If FD_IN is asserted when RFFD is Low, the behavior of the core is not specified
c_{Block Size Select (BLOCK_SIZE_SEL)}
o ^{This 4-bit port determines the size of the block of data to be written into the encoder. The block size}
select value is sampled on an active rising clock edge when FD_IN is High and ND (if selected) is High.
If an invalid block size select code (not in the range 0-12) is sampled, the behavior of the core is not
n _specified.
Ready For First Data (RFFD)
t _{When this output is asserted High, it indicates that the core is ready to accept an FD_IN signal to start}
i _{a new encoding operation. When a valid-FD signal is sampled, the RFFD signal goes Low and remains}
n _{Low until it is safe to start another block.}
Ready For Data (RFD)
u _{When this pin is asserted High, it indicates that the core is ready to accept new input data. If RFD is}
selected, then it is High during the period that a particular block is input. When block size samples of
e _{data have been input, the RFD signal goes Low to indicate that the core is no longer ready to accept}
data.
d _{RSC1 Systematic Output (RSC1_SYSTEMATIC)}
RSC1_SYSTEMATIC is a delayed version of the uninterleaved input data. During trellis termination,
the RSC1_SYSTEMATIC port also carries systematic and parity tail bits.
IP _{RSC1 Parity0 Output (RSC1_PARITY0)}
RSC1_PARITY0 is the Y0 output from RSC1. (See Figure 3.)
RSC1 Parity1 Output (RSC1_PARITY1)
RSC1_PARITY1 is the Y1 output from RSC1. (See Figure 3.)
RSC2 Systematic Output (RSC2_SYSTEMATIC)
RSC2_SYSTEMATIC is a delayed and interleaved version of the input data. This output is provided for
diagnostic purposes. It is normally left unconnected.
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DS604 April 2, 2007
Product Specification