DS604 Datasheet, PDF (3/12 Pages) –

3GPP2 Turbo Encoder v2.0
Recursive Systematic Convolution (RSC) Encoder Structure
The schematic for each of the two RSCs and the transfer functions for the outputs are shown in Figure 3.
Figure Top x-ref 3
S ystem a tic(X)
+
Par ity0( Y ₀)
D Input bits (X)
+
SW1
delay
delay
delay
+
Parity1(Y1)
isc _{X(D) = 1}
Y ₀( D)
=
--1----+-----D------+-----D----³--
1 + D² + D³
+
Y ₁( D)
=
-1----+-----D-----+------D----²----+----D-----³-
1 + D² + D ³
Figure 3: TCC RSC Structure
DS604_03_011807
o _{After a block of input data has been coded, the RSCs must return to the initial zero state. To force the}
RSC back to the all zero state, the input value is set equal to the feedback value by setting the control
n _{switch, SW1, to the lower position for three clock cycles.}
During the first three tail bit periods, RSC2 is disabled, and the control switch of RSC1 is set to the lower
t _{position to output the RSC1 tail bits on the RSC1 systematic and parity outputs.}
in _{During the last three tail bit periods, RSC1 is disabled and the control switch of RSC2 is set to the lower}
position to output the RSC2 tail bits on the RSC2 systematic and parity outputs. The RSC2 systematic
tail bits are duplicated on the RSC1_SYSTEMATIC output. This avoids the need for the user to connect
u _{the RSC2_SYSTEMATIC port.}
Block Size Selection
e _{The encoding sequence is initiated from a single First Data (FD) pulse. When a valid FD is detected, the}
block or frame size is determined by the 4-bit code on the BLOCK_SIZE_SEL input.
d _{The values of BLOCK_SIZE_SEL for all of the 3GPP2 valid block sizes are shown in Table 1.}
Table 1: Block Size Select Codes
IP BLOCK_SIZE_SEL
Turbo Encoder Block Size
0
0000
122
1
0001
250
2
0010
506
3
0011
762
4
0100
1018
5
0101
1530
6
0110
2042
7
0111
3066
DS604 April 2, 2007
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Product Specification