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XC4VLX15_08 Datasheet, PDF (8/56 Pages) Xilinx, Inc – Virtex-4 FPGA Data Sheet | |||
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Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
SelectIO⢠DC Input and Output Levels
Values for VIL and VIH are recommended input voltages.
Values for IOL and IOH are guaranteed over the recom-
mended operating conditions at the VOL and VOH test
points. Only selected standards are tested. These are cho-
sen to ensure that all standards meet their specifications.
The selected standards are tested at a minimum VCCO with
the respective VOL and VOH voltage levels shown. Other
standards are sample tested.
Table 7: SelectIO DC Input and Output Levels
IOSTANDARD
Attribute
V, Min
VIL
V, Max
VIH
V, Min
V, Max
VOL
V, Max
VOH
V, Min
IOL
IOH
mA mA
LVTTL
â0.2
0.8
2.0
3.45
0.4
2.4
Note(3) Note(3)
LVCMOS33,
LVDCI33
â0.2
0.8
2.0
3.45
0.4
VCCO â 0.4 Note(3) Note(3)
LVCMOS25,
LVDCI25
â0.3
0.7
1.7
VCCO + 0.3
0.4
VCCO â 0.4 Note(3) Note(3)
LVCMOS18,
LVDCI18
â0.3
35% VCCO
65% VCCO VCCO + 0.3
0.4
VCCO â 0.45 Note(4) Note(4)
LVCMOS15,
LVDCI15
â0.3
35% VCCO
65% VCCO VCCO + 0.3
0.4
VCCO â 0.45 Note(4) Note(4)
PCI33_3(5)
PCI66_3(5)
PCI-X(5)
â0.2
â0.2
â0.2
30% VCCO
30% VCCO
35% VCCO
50% VCCO
50% VCCO
50% VCCO
VCCO
10% VCCO 90% VCCO
1.5
VCCO
10% VCCO 90% VCCO
1.5
VCCO
10% VCCO 90% VCCO
1.5
GTLP
â0.3
VREF â 0.1
VREF + 0.1
â
0.6
N/A
36
GTL
HSTL I(2)
â0.3 VREF â 0.05 VREF + 0.05
â
0.4
â0.3
VREF â 0.1
VREF + 0.1 VCCO + 0.3
0.4
N/A
32
VCCO â 0.4
8
HSTL II(2)
â0.3
VREF â 0.1
VREF + 0.1 VCCO + 0.3
0.4
VCCO â 0.4
16
HSTL III(2)
HSTL IV(2)
â0.3
VREF â 0.1
VREF + 0.1 VCCO + 0.3
0.4
â0.3
VREF â 0.1
VREF + 0.1 VCCO + 0.3
0.4
VCCO â 0.4
24
VCCO â 0.4
48
DIFF HSTL II(2)
â0.3
50%
VCCO â 0.1
50%
VCCO + 0.1
VCCO + 0.3
0.4
VCCO â 0.4
â
SSTL2 I
â0.3 VREF â 0.15 VREF + 0.15 VCCO + 0.3 VTT â 0.61 VTT + 0.61
8.1
SSTL2 II
â0.3 VREF â 0.15 VREF + 0.15 VCCO + 0.3 VTT â 0.81 VTT + 0.81 16.2
DIFF SSTL2 II
â0.3
50%
VCCO â 0.15
50%
VCCO + 0.15
VCCO + 0.3
0.5
VCCO â 0.5
â
SSTL18 I
â0.3 VREF â 0.125 VREF + 0.125 VCCO + 0.3 VTT â 0.47 VTT + 0.47
6.7
SSTL18 II
â0.3 VREF â 0.125 VREF + 0.125 VCCO + 0.3 VTT â 0.60 VTT + 0.60 13.4
DIFF SSTL18 II
â0.3
50%
VCCO â 0.125
50%
VCCO + 0.125
VCCO + 0.3
0.4
VCCO â 0.4
â
Notes:
1. Tested according to relevant specifications.
2. Applies to both 1.5V and 1.8V HSTL.
3. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
4. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
5. For more information on PCI33_3, PCI66_3, and PCI-X, refer to the Virtex-4 FPGA User Guide, SelectIO Resources, Chapter 6.
â0.5
â0.5
â0.5
N/A
N/A
â8
â16
â8
â8
â
â8.1
â16.2
â
â6.7
â13.4
â
DS302 (v3.2) April 10, 2008
www.xilinx.com
Product Specification
8
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