XC4VLX15_08 Datasheet, PDF (32/56 Pages) Xilinx, Inc – Virtex-4 FPGA Data Sheet

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Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 40: Block RAM Switching Characteristics
Speed Grade
Symbol
Description
-12
-11
-10
Units
Sequential Delays
T_{RCKO_DORA}
T_{RCKO_DOA}
Clock CLK to DOUT output (without output register)⁽²⁾ 1.65
1.83
2.10
ns, Max
Clock CLK to DOUT output with ECC
(without output register)
3.00
3.33
3.83
ns, Max
Clock CLK to DOUT output (with output register)⁽³⁾
0.72
0.80
0.92
ns, Min
Clock CLK to DOUT output with ECC (with output
register)
2.00
2.20
2.50
ns, Max
Setup and Hold Times Before Clock CLK
T_{RCCK_ADDR} / T_{RCKC_ADDR}
ADDR inputs
0.34
0.37
0.43
0.26
0.28
0.33
ns, Min
T_{RDCK_DI} / T_{RCKD_DI}
DIN inputs⁽⁴⁾
0.18
0.20
0.23
0.26
0.28
0.33
ns, Min
T_{RCCK_EN} / T_{RCKC_EN}
EN input⁽⁵⁾
0.41
0.45
0.52
0.26
0.28
0.33
ns, Min
T_{RCCK_REGCE} / T_{RCKC_REGCE} CE input of output register
0.25
0.27
0.32
0.26
0.28
0.33
ns, Min
T_{RCCK_SSR} / T_{RCKC_SSR}
RST input
0.25
0.27
0.32
0.26
0.28
0.33
ns, Min
T_{RCCK_WE} / T_{RCKC_WE}
WEN input
0.59
0.65
0.75
0.26
0.28
0.33
ns, Min
Maximum Frequency
F_MAX
F_MAX
CLK-to-CLK
Write first and no change mode
Read first mode
Read first mode
500.00
500.00
500.00
450.45
450.45
450.45
400.00
400.00
400.00
MHz
MHz
MHz
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2. T_{RCKO_DORA} includes T_{RCKO_DOWA}, T_{RCKO_DOPAR}, and T_{RCKO_DOPAW} as well as the B port equivalent timing parameters.
3. T_{RCKO_DOA} includes T_{RCKO_DOPA} as well as the B port equivalent timing parameters.
4. T_{RCKO_DI} includes both A and B inputs as well as the parity inputs of A and B.
5. Xilinx block RAMs do not have asynchronous inputs on an enabled port address. During the time that a port is enabled, its addresses must be stable
during the specified set-up time. Do not create an asynchronous input on an enabled port address.
DS302 (v3.2) April 10, 2008
www.xilinx.com
Product Specification
32