XC4VLX15_08 Datasheet, PDF (29/56 Pages) Xilinx, Inc – Virtex-4 FPGA Data Sheet

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Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Input Delay Switching Characteristics
Table 35: Input Delay Switching Characteristics
Speed Grade
Symbol
Description
-12
-11
-10
Units
T_{IDELAYRESOLUTION}
T_{IDELAYTOTAL_ERR}
IDELAY Chain Delay Resolution
Cumulative delay at a given tap⁽²⁾
75
75
75
ps
[(tap −1) x 75 +34]
± 0.07[(tap −1) x 75 +34]
ps
T_{IDELAYCTRLCO_RDY}
Reset to Ready for IDELAYCTRL
(Maximum)
3.00
3.00
3.00
µs
F_{IDELAYCTRL_REF}
IDELAYCTRL_REF_PRECISION ⁽³⁾
REFCLK frequency
REFCLK precision
200
200
200
MHz
±10
±10
±10
MHz
T_{IDELAYCTRL_RPW}
T_{IDELAYPAT_JIT}
Minimum Reset pulse width
Pattern dependent period jitter in delay
chain for clock pattern
Pattern dependent period jitter in delay
chain for random data pattern (PRBS 23)
50.0
0
10 ± 2
50.0
0
10 ± 2
50.0
0
10 ± 2
ns
Note (4)
Note (4)
Notes:
1. Refer to Xilinx Application Note XAPP707 for details on IDELAY timing characteristics.
2. This value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps.
3. See the “REFCLK - Reference Clock” section (specific to IDELAYCTRL) in the Virtex-4 FPGA User Guide: Chapter 7, SelectIO Logic Resources.
4. Units in ps peak-to-peak per tap.
Output Serializer/Deserializer Switching Characteristics
Table 36: OSERDES Switching Characteristics
Symbol
Setup/Hold
T_{OSDCK_D} / T_{OSCKD_D}
Description
D input Setup/Hold with respect to CLKDIV
T_{OSDCK_T} / T_{OSCKD_T(1)}
T input Setup/Hold with respect to CLK
T_{OSDCK_T2} / T_{OSCKD_T2(1)}
T input Setup/Hold with respect to CLKDIV
T_{OSCCK_OCE} / T_{OSCKC_OCE} OCE input Setup/Hold with respect to CLK
T_{OSCCK_S}
SR (Reset) input Setup with respect to CLKDIV
T_{OSCCK_TCE} / T_{OSCKC_TCE}
TCE input Setup/Hold with respect to CLK
Sequential Delays
T_{OSCKO_OQ}
T_{OSCKO_TQ}
Combinatorial
Clock to out from CLK to OQ
Clock to out from CLK to TQ
T_{OSDO_TTQ}
T input to TQ Out
T_{OSCO_OQ}
Asynchronous Reset to OQ
T_{OSCO_TQ}
Asynchronous Reset to TQ
Notes:
1. T_{OSDCK_T2} and T_{OSCKD_T2} are reported as T_{OSDCK_T} / T_{OSCKD_T} in TRCE report.
Speed Grade
-12
-11
-10
Units
0.35
–0.05
0.42
–0.04
0.50
–0.03
ns
0.43
–0.16
0.52
–0.16
0.62
–0.16
ns
0.35
–0.05
0.42
–0.04
0.50
–0.03
ns
0.45
0.01
0.53
0.02
0.64
0.03
ns
0.67
0.80
0.96
ns
0.45
0.01
0.53
0.02
0.64
0.03
ns
0.41
0.49
0.59
ns
0.41
0.49
0.59
ns
0.56
0.65
0.76
ns
1.14
1.37
1.64
ns
1.14
1.37
1.64
ns
DS302 (v3.2) April 10, 2008
www.xilinx.com
Product Specification
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