XC4VLX15_08 Datasheet, PDF (44/56 Pages) Xilinx, Inc – Virtex-4 FPGA Data Sheet

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Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 55: Global Clock Input to Output Delay for LVCMOS25 Standard, 12 mA, Fast Slew Rate, without DCM
Symbol
Description
Device
Speed Grade
-12
-11
-10
Units
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12 mA, Fast Slew Rate, without DCM.
T_ICKOF
Global Clock and OFF without DCM
XC4VLX15
6.42
7.22
8.14
ns
XC4VLX25
6.50
7.32
8.25
ns
XC4VLX40
6.70
7.54
8.50
ns
XC4VLX60
6.86
7.72
8.70
ns
XC4VLX80
6.98
7.85
8.85
ns
XC4VLX100 7.23
8.15
9.18
ns
XC4VLX160 7.46
8.40
9.46
ns
XC4VLX200
N/A
8.79
9.88
ns
XC4VSX25
6.69
7.52
8.47
ns
XC4VSX35
6.75
7.59
8.56
ns
XC4VSX55
7.10
7.99
9.00
ns
XC4VFX12
6.41
7.21
8.13
ns
XC4VFX20
6.60
7.42
8.37
ns
XC4VFX40
6.97
7.84
8.83
ns
XC4VFX60
6.98
7.86
8.85
ns
XC4VFX100 7.46
8.40
9.45
ns
XC4VFX140
N/A
8.80
9.90
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
DS302 (v3.2) April 10, 2008
www.xilinx.com
Product Specification
44